[TG3]: Add TG3_FLAG_SUPPORT_MSI flag.
And fix up the code to always allow MSI on 5714 A2. Call tg3_find_peer() earlier because we need that information before we can determine whether we can set TG3_FLAG_SUPPORT_MSI or not. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -7033,11 +7033,7 @@ static int tg3_open(struct net_device *dev)
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if (err)
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return err;
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if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
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(GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
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(GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
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!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
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(tp->pdev_peer == tp->pdev))) {
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if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
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/* All MSI supporting chips should support tagged
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* status. Assert that this is the case.
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*/
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@ -10404,6 +10400,8 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
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}
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}
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static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
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static int __devinit tg3_get_invariants(struct tg3 *tp)
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{
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static struct pci_device_id write_reorder_chipsets[] = {
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@ -10559,6 +10557,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
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tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
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tp->pdev_peer = tg3_find_peer(tp);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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@ -10572,6 +10574,14 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
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if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
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GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
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tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
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tp->pdev_peer == tp->pdev))
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tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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@ -11897,10 +11907,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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tp->rx_pending = 63;
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}
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
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tp->pdev_peer = tg3_find_peer(tp);
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err = tg3_get_device_address(tp);
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if (err) {
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printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
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@ -131,6 +131,7 @@
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#define CHIPREV_ID_5752_A0_HW 0x5000
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#define CHIPREV_ID_5752_A0 0x6000
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#define CHIPREV_ID_5752_A1 0x6001
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#define CHIPREV_ID_5714_A2 0x9002
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#define CHIPREV_ID_5906_A1 0xc001
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#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
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#define ASIC_REV_5700 0x07
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@ -2221,6 +2222,7 @@ struct tg3 {
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#define TG3_FLAG_IN_RESET_TASK 0x04000000
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#define TG3_FLAG_40BIT_DMA_BUG 0x08000000
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#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
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#define TG3_FLAG_SUPPORT_MSI 0x20000000
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#define TG3_FLAG_CHIP_RESETTING 0x40000000
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#define TG3_FLAG_INIT_COMPLETE 0x80000000
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u32 tg3_flags2;
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