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gpio: dt-bindings: document the concept of GPIO banks 

Cc: devicetree@vger.kernel.org
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
steinar/wifi_calib_4_9_kernel
Linus Walleij 2016-03-31 11:09:11 +02:00
parent dd98756d78
commit 75c004df52
1 changed files with 14 additions and 0 deletions
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14
Documentation/devicetree/bindings/gpio/gpio.txt
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@ -131,6 +131,19 @@ Every GPIO controller node must contain both an empty "gpio-controller"
property, and a #gpio-cells integer property, which indicates the number of
cells in a gpio-specifier.
Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
instance of a hardware IP core on a silicon die, usually exposed to the
programmer as a coherent range of I/O addresses. Usually each such bank is
exposed in the device tree as an individual gpio-controller node, reflecting
the fact that the hardware was synthesized by reusing the same IP block a
few times over.
A GPIO controller may specify a bank ID. This is a hardware index that
indicate the logical order of the GPIO controller in the hardware architecture,
usually in the sequence 0, 1, 2 .. n. The hardware index may be different
from the order of register ranges and related to the backplane of how this
one bank is connected to the outside through a pin controller for example.
Optionally, a GPIO controller may have a "ngpios" property. This property
indicates the number of in-use slots of available slots for GPIOs. The
typical example is something like this: the hardware register is 32 bits
@ -152,6 +165,7 @@ gpio-controller@00000000 {
reg = <0x00000000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <0>;
ngpios = <18>;
}