drm/i915: Kill most of the FBC register save/restore
We will anyway re-enable FBC normally after resume, so trying to save and restore the register makes little sense. We do need to preserve the FBC1 interval bits in FBC_CONTROL since we only initialize them during driver load, and try to preserve them after that. v2: s/I915_HAS_FBC/HAS_FBC/ and fix the check for gen4 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -859,11 +859,7 @@ struct i915_suspend_saved_registers {
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u32 savePFIT_CONTROL;
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u32 save_palette_a[256];
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u32 save_palette_b[256];
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u32 saveDPFC_CB_BASE;
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u32 saveFBC_CFB_BASE;
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u32 saveFBC_LL_BASE;
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u32 saveFBC_CONTROL;
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u32 saveFBC_CONTROL2;
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u32 saveIER;
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u32 saveIIR;
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u32 saveIMR;
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@ -236,19 +236,9 @@ static void i915_save_display(struct drm_device *dev)
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dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
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}
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/* Only regfile.save FBC state on the platform that supports FBC */
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if (HAS_FBC(dev)) {
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if (HAS_PCH_SPLIT(dev)) {
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dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
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} else if (IS_GM45(dev)) {
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dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
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} else {
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dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
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dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
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dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
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dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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}
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}
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/* save FBC interval */
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if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
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dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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if (!drm_core_check_feature(dev, DRIVER_MODESET))
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i915_save_vga(dev);
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@ -300,18 +290,10 @@ static void i915_restore_display(struct drm_device *dev)
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/* only restore FBC info on the platform that supports FBC*/
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intel_disable_fbc(dev);
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if (HAS_FBC(dev)) {
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if (HAS_PCH_SPLIT(dev)) {
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I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
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} else if (IS_GM45(dev)) {
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I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
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} else {
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I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
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I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
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I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
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I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
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}
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}
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/* restore FBC interval */
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if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
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I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
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if (!drm_core_check_feature(dev, DRIVER_MODESET))
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i915_restore_vga(dev);
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