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iommu/tegra: gart: Fix register offset correctly

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DT passes the exact GART register ranges without any overlapping with
MC register ranges. GART register offset needs to be adjusted by one
passed by DT correctly.

Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
Hiroshi DOYU 2012-05-10 10:45:32 +03:00 committed by Joerg Roedel
parent 7cffae421e
commit 774dfc9bb7
2 changed files with 7 additions and 6 deletions
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6
Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
View file

@ -7,8 +7,8 @@ Required properties:
Example:
gart: gart@7000f000 {
gart {
compatible = "nvidia,tegra20-gart";
reg = < 0x7000f000 0x00000100 /* controller registers */
0x58000000 0x02000000 >; /* GART aperture */
reg = <0x7000f024 0x00000018 /* controller registers */
0x58000000 0x02000000>; /* GART aperture */
};

7
drivers/iommu/tegra-gart.c
View file

@ -36,9 +36,10 @@
/* bitmap of the page sizes currently supported */
#define GART_IOMMU_PGSIZES (SZ_4K)
#define GART_CONFIG 0x24
#define GART_ENTRY_ADDR 0x28
#define GART_ENTRY_DATA 0x2c
#define GART_REG_BASE 0x24
#define GART_CONFIG (0x24 - GART_REG_BASE)
#define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
#define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31)
#define GART_PAGE_SHIFT 12