PCI: Add and use standard PCI-X Capability register names
Add and use #defines for PCI-X Capability registers and fields. Note that the PCI-X Capability has a different layout for type 0 (endpoint) and type 1 (bridge) devices. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -579,14 +579,16 @@ static void pci_set_bus_speed(struct pci_bus *bus)
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if (pos) {
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u16 status;
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enum pci_bus_speed max;
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pci_read_config_word(bridge, pos + 2, &status);
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if (status & 0x8000) {
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pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
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&status);
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if (status & PCI_X_SSTATUS_533MHZ) {
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max = PCI_SPEED_133MHz_PCIX_533;
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} else if (status & 0x4000) {
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} else if (status & PCI_X_SSTATUS_266MHZ) {
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max = PCI_SPEED_133MHz_PCIX_266;
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} else if (status & 0x0002) {
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if (((status >> 12) & 0x3) == 2) {
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} else if (status & PCI_X_SSTATUS_133MHZ) {
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if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) {
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max = PCI_SPEED_133MHz_PCIX_ECC;
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} else {
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max = PCI_SPEED_133MHz_PCIX;
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@ -596,7 +598,8 @@ static void pci_set_bus_speed(struct pci_bus *bus)
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}
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bus->max_bus_speed = max;
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bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
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bus->cur_bus_speed = pcix_bus_speed[
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(status & PCI_X_SSTATUS_FREQ) >> 6];
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return;
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}
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@ -349,7 +349,7 @@
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#define PCI_AF_STATUS_TP 0x01
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#define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */
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/* PCI-X registers */
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/* PCI-X registers (Type 0 (non-bridge) devices) */
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#define PCI_X_CMD 2 /* Modes & Features */
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#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
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@ -389,6 +389,19 @@
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#define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */
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#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */
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/* PCI-X registers (Type 1 (bridge) devices) */
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#define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */
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#define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */
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#define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */
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#define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */
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#define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */
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#define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */
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#define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */
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#define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */
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#define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */
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#define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */
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/* PCI Bridge Subsystem ID registers */
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#define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */
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