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ASoC: tlv320aic32x4: Use correct shift definition for DATALEN bits

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Setting the DATALEN bit field requires shifting our value by 4. Setting
the OSR value of the PLL divider also requires a shift by 4. Currently
the code abuses this fact and uses the shift for the divider register to
set the data-length register. Fix this here by using the definition meant
for this register.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Andrew F. Davis 2017-12-12 16:43:06 -06:00 committed by Mark Brown
parent 4483521d81
commit 77bdb58795
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GPG key ID: 24D68B725D5487D0
1 changed files with 8 additions and 3 deletions
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11
sound/soc/codecs/tlv320aic32x4.c
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@ -738,15 +738,20 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
data = data & ~(3 << 4);
switch (params_width(params)) {
case 16:
data |= (AIC32X4_WORD_LEN_16BITS <<
AIC32X4_IFACE1_DATALEN_SHIFT);
break;
case 20:
data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
data |= (AIC32X4_WORD_LEN_20BITS <<
AIC32X4_IFACE1_DATALEN_SHIFT);
break;
case 24:
data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
data |= (AIC32X4_WORD_LEN_24BITS <<
AIC32X4_IFACE1_DATALEN_SHIFT);
break;
case 32:
data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
data |= (AIC32X4_WORD_LEN_32BITS <<
AIC32X4_IFACE1_DATALEN_SHIFT);
break;
}
snd_soc_write(codec, AIC32X4_IFACE1, data);