ASoC: tlv320aic32x4: Use correct shift definition for DATALEN bits
Setting the DATALEN bit field requires shifting our value by 4. Setting the OSR value of the PLL divider also requires a shift by 4. Currently the code abuses this fact and uses the shift for the divider register to set the data-length register. Fix this here by using the definition meant for this register. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -738,15 +738,20 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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data = data & ~(3 << 4);
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switch (params_width(params)) {
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case 16:
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data |= (AIC32X4_WORD_LEN_16BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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break;
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case 20:
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data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
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data |= (AIC32X4_WORD_LEN_20BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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break;
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case 24:
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data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
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data |= (AIC32X4_WORD_LEN_24BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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break;
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case 32:
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data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
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data |= (AIC32X4_WORD_LEN_32BITS <<
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AIC32X4_IFACE1_DATALEN_SHIFT);
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break;
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}
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snd_soc_write(codec, AIC32X4_IFACE1, data);
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