sh: IPR IRQ updates for SH7619/SH7206.
This updates the SH7619 and SH7206 code for the IPR IRQ changes. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Yoshinori Sato
Paul Mundt
parent
ff4e2ca7c6
commit
780a156888
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@ -10,6 +10,7 @@
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/se7206.h>
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#define INTSTS0 0x31800000
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@ -18,6 +19,13 @@
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#define INTMSK1 0x31800006
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#define INTSEL 0x31800008
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#define IRQ0_IRQ 64
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#define IRQ1_IRQ 65
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#define IRQ3_IRQ 67
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#define INTC_IPR01 0xfffe0818
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#define INTC_ICR1 0xfffe0802
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static void disable_se7206_irq(unsigned int irq)
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{
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unsigned short val;
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@ -39,7 +47,7 @@ static void disable_se7206_irq(unsigned int irq)
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case IRQ1_IRQ:
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msk0 |= 0x000f;
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break;
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case IRQ2_IRQ:
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case IRQ3_IRQ:
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msk0 |= 0x0f00;
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msk1 |= 0x00ff;
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break;
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@ -70,7 +78,7 @@ static void enable_se7206_irq(unsigned int irq)
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case IRQ1_IRQ:
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msk0 &= ~0x000f;
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break;
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case IRQ2_IRQ:
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case IRQ3_IRQ:
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msk0 &= ~0x0f00;
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msk1 &= ~0x00ff;
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break;
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@ -96,7 +104,7 @@ static void eoi_se7206_irq(unsigned int irq)
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case IRQ1_IRQ:
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sts0 &= ~0x000f;
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break;
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case IRQ2_IRQ:
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case IRQ3_IRQ:
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sts0 &= ~0x0f00;
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sts1 &= ~0x00ff;
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break;
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@ -106,7 +114,7 @@ static void eoi_se7206_irq(unsigned int irq)
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}
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static struct irq_chip se7206_irq_chip __read_mostly = {
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.name = "SE7206-FPGA-IRQ",
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.name = "SE7206-FPGA",
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.mask = disable_se7206_irq,
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.unmask = enable_se7206_irq,
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.mask_ack = disable_se7206_irq,
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@ -51,3 +51,44 @@ static int __init sh7619_devices_setup(void)
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ARRAY_SIZE(sh7619_devices));
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}
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__initcall(sh7619_devices_setup);
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#define INTC_IPRC 0xf8080000UL
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#define INTC_IPRD 0xf8080002UL
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#define CMI0_IRQ 86
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#define SCIF0_ERI_IRQ 88
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#define SCIF0_RXI_IRQ 89
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#define SCIF0_BRI_IRQ 90
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#define SCIF0_TXI_IRQ 91
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#define SCIF1_ERI_IRQ 92
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#define SCIF1_RXI_IRQ 93
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#define SCIF1_BRI_IRQ 94
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#define SCIF1_TXI_IRQ 95
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#define SCIF2_BRI_IRQ 96
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#define SCIF2_ERI_IRQ 97
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#define SCIF2_RXI_IRQ 98
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#define SCIF2_TXI_IRQ 99
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static struct ipr_data sh7619_ipr_map[] = {
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{ CMI0_IRQ, INTC_IPRC, 1, 2 },
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{ SCIF0_ERI_IRQ, INTC_IPRD, 3, 3 },
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{ SCIF0_RXI_IRQ, INTC_IPRD, 3, 3 },
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{ SCIF0_BRI_IRQ, INTC_IPRD, 3, 3 },
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{ SCIF0_TXI_IRQ, INTC_IPRD, 3, 3 },
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{ SCIF1_ERI_IRQ, INTC_IPRD, 2, 3 },
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{ SCIF1_RXI_IRQ, INTC_IPRD, 2, 3 },
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{ SCIF1_BRI_IRQ, INTC_IPRD, 2, 3 },
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{ SCIF1_TXI_IRQ, INTC_IPRD, 2, 3 },
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{ SCIF2_ERI_IRQ, INTC_IPRD, 1, 3 },
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{ SCIF2_RXI_IRQ, INTC_IPRD, 1, 3 },
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{ SCIF2_BRI_IRQ, INTC_IPRD, 1, 3 },
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{ SCIF2_TXI_IRQ, INTC_IPRD, 1, 3 },
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};
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void __init init_IRQ_ipr(void)
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{
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make_ipr_irq(sh7619_ipr_map, ARRAY_SIZE(sh7619_ipr_map));
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}
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@ -17,22 +17,22 @@ static struct plat_sci_port sci_platform_data[] = {
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.mapbase = 0xfffe8000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 240, 241, 242, 243},
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.irqs = { 241, 242, 243, 240},
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}, {
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.mapbase = 0xfffe8800,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 244, 245, 246, 247},
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.irqs = { 247, 244, 245, 246},
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}, {
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.mapbase = 0xfffe9000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 248, 249, 250, 251},
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.irqs = { 249, 250, 251, 248},
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}, {
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.mapbase = 0xfffe9800,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 252, 253, 254, 255},
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.irqs = { 253, 254, 255, 252},
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}, {
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.flags = 0,
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}
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@ -56,3 +56,57 @@ static int __init sh7206_devices_setup(void)
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ARRAY_SIZE(sh7206_devices));
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}
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__initcall(sh7206_devices_setup);
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#define INTC_IPR08 0xfffe0c04UL
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#define INTC_IPR09 0xfffe0c06UL
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#define INTC_IPR14 0xfffe0c10UL
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#define CMI0_IRQ 140
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#define MTU1_TGI1A 164
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#define SCIF0_BRI_IRQ 240
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#define SCIF0_ERI_IRQ 241
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#define SCIF0_RXI_IRQ 242
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#define SCIF0_TXI_IRQ 243
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#define SCIF1_BRI_IRQ 244
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#define SCIF1_ERI_IRQ 245
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#define SCIF1_RXI_IRQ 246
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#define SCIF1_TXI_IRQ 247
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#define SCIF2_BRI_IRQ 248
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#define SCIF2_ERI_IRQ 249
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#define SCIF2_RXI_IRQ 250
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#define SCIF2_TXI_IRQ 251
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#define SCIF3_BRI_IRQ 252
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#define SCIF3_ERI_IRQ 253
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#define SCIF3_RXI_IRQ 254
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#define SCIF3_TXI_IRQ 255
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static struct ipr_data sh7206_ipr_map[] = {
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{ CMI0_IRQ, INTC_IPR08, 3, 2 },
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{ MTU2_TGI1A, INTC_IPR09, 1, 2 },
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{ SCIF0_ERI_IRQ, INTC_IPR14, 3, 3 },
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{ SCIF0_RXI_IRQ, INTC_IPR14, 3, 3 },
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{ SCIF0_BRI_IRQ, INTC_IPR14, 3, 3 },
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{ SCIF0_TXI_IRQ, INTC_IPR14, 3, 3 },
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{ SCIF1_ERI_IRQ, INTC_IPR14, 2, 3 },
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{ SCIF1_RXI_IRQ, INTC_IPR14, 2, 3 },
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{ SCIF1_BRI_IRQ, INTC_IPR14, 2, 3 },
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{ SCIF1_TXI_IRQ, INTC_IPR14, 2, 3 },
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{ SCIF2_ERI_IRQ, INTC_IPR14, 1, 3 },
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{ SCIF2_RXI_IRQ, INTC_IPR14, 1, 3 },
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{ SCIF2_BRI_IRQ, INTC_IPR14, 1, 3 },
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{ SCIF2_TXI_IRQ, INTC_IPR14, 1, 3 },
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{ SCIF3_ERI_IRQ, INTC_IPR14, 0, 3 },
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{ SCIF3_RXI_IRQ, INTC_IPR14, 0, 3 },
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{ SCIF3_BRI_IRQ, INTC_IPR14, 0, 3 },
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{ SCIF3_TXI_IRQ, INTC_IPR14, 0, 3 },
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};
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void __init init_IRQ_ipr(void)
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{
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make_ipr_irq(sh7206_ipr_map, ARRAY_SIZE(sh7206_ipr_map));
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}
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