bnx2x: Fix CL73 autoneg issues
- Advertise 1G KX4 in CL73 when 1G speed capability is enabled - Add flow-control negotiation over CL73 - External loopback test on Serdes should be done in FORCE mode, since in CL73 it is unable to link up with the same core using AUTONEG - Fix bnx2x_set_led function to support CL73 link leds Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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commit
7846e471b5
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@ -1228,7 +1228,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
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params->phy_addr,
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params->phy_addr,
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MDIO_REG_BANK_CL73_USERB0,
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MDIO_REG_BANK_CL73_USERB0,
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MDIO_CL73_USERB0_CL73_UCTRL,
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MDIO_CL73_USERB0_CL73_UCTRL,
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MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL);
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0xe);
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/* Enable BAM Station Manager*/
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/* Enable BAM Station Manager*/
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CL45_WR_OVER_CL22(bp, params->port,
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CL45_WR_OVER_CL22(bp, params->port,
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@ -1239,29 +1239,25 @@ static void bnx2x_set_autoneg(struct link_params *params,
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MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
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MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
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MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
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MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
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/* Merge CL73 and CL37 aneg resolution */
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/* Advertise CL73 link speeds */
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_USERB0,
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MDIO_CL73_USERB0_CL73_BAM_CTRL3,
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®_val);
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if (params->speed_cap_mask &
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PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
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/* Set the CL73 AN speed */
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CL45_RD_OVER_CL22(bp, params->port,
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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params->phy_addr,
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MDIO_REG_BANK_CL73_IEEEB1,
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MDIO_REG_BANK_CL73_IEEEB1,
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MDIO_CL73_IEEEB1_AN_ADV2,
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MDIO_CL73_IEEEB1_AN_ADV2,
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®_val);
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®_val);
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if (params->speed_cap_mask &
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PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
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reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
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if (params->speed_cap_mask &
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PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
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reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
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CL45_WR_OVER_CL22(bp, params->port,
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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params->phy_addr,
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MDIO_REG_BANK_CL73_IEEEB1,
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MDIO_REG_BANK_CL73_IEEEB1,
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MDIO_CL73_IEEEB1_AN_ADV2,
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MDIO_CL73_IEEEB1_AN_ADV2,
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reg_val | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4);
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reg_val);
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}
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/* CL73 Autoneg Enabled */
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/* CL73 Autoneg Enabled */
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reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
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reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
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@ -1389,12 +1385,23 @@ static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
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u16 ieee_fc)
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u16 ieee_fc)
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{
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{
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struct bnx2x *bp = params->bp;
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struct bnx2x *bp = params->bp;
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u16 val;
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/* for AN, we are always publishing full duplex */
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/* for AN, we are always publishing full duplex */
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CL45_WR_OVER_CL22(bp, params->port,
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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params->phy_addr,
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MDIO_REG_BANK_COMBO_IEEE0,
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MDIO_REG_BANK_COMBO_IEEE0,
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_IEEEB1,
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MDIO_CL73_IEEEB1_AN_ADV1, &val);
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val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
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val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
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CL45_WR_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_IEEEB1,
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MDIO_CL73_IEEEB1_AN_ADV1, val);
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}
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}
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static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
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static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
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@ -1630,21 +1637,49 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
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(!(vars->phy_flags & PHY_SGMII_FLAG)) &&
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(!(vars->phy_flags & PHY_SGMII_FLAG)) &&
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(XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
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(XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
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CL45_RD_OVER_CL22(bp, params->port,
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if ((gp_status &
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params->phy_addr,
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(MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
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MDIO_REG_BANK_COMBO_IEEE0,
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MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
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(MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
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&ld_pause);
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MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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CL45_RD_OVER_CL22(bp, params->port,
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MDIO_REG_BANK_COMBO_IEEE0,
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params->phy_addr,
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MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
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MDIO_REG_BANK_CL73_IEEEB1,
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&lp_pause);
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MDIO_CL73_IEEEB1_AN_ADV1,
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pause_result = (ld_pause &
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&ld_pause);
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_CL73_IEEEB1,
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MDIO_CL73_IEEEB1_AN_LP_ADV1,
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&lp_pause);
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pause_result = (ld_pause &
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MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
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>> 8;
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pause_result |= (lp_pause &
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MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
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>> 10;
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DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
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pause_result);
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} else {
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_COMBO_IEEE0,
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
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&ld_pause);
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CL45_RD_OVER_CL22(bp, params->port,
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params->phy_addr,
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MDIO_REG_BANK_COMBO_IEEE0,
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MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
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&lp_pause);
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pause_result = (ld_pause &
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
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pause_result |= (lp_pause &
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pause_result |= (lp_pause &
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
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DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
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DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
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pause_result);
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}
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bnx2x_pause_resolve(vars, pause_result);
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bnx2x_pause_resolve(vars, pause_result);
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} else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
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} else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
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(bnx2x_ext_phy_resolve_fc(params, vars))) {
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(bnx2x_ext_phy_resolve_fc(params, vars))) {
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@ -1990,8 +2025,7 @@ static u8 bnx2x_emac_program(struct link_params *params,
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GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
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GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
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mode);
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mode);
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bnx2x_set_led(bp, params->port, LED_MODE_OPER,
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bnx2x_set_led(params, LED_MODE_OPER, line_speed);
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line_speed, params->hw_led_mode, params->chip_id);
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return 0;
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return 0;
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}
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}
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@ -3547,7 +3581,10 @@ static void bnx2x_init_internal_phy(struct link_params *params,
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bnx2x_set_preemphasis(params);
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bnx2x_set_preemphasis(params);
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/* forced speed requested? */
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/* forced speed requested? */
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if (vars->line_speed != SPEED_AUTO_NEG) {
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if (vars->line_speed != SPEED_AUTO_NEG ||
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((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
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params->loopback_mode == LOOPBACK_EXT)) {
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DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
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DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
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/* disable autoneg */
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/* disable autoneg */
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@ -5731,13 +5768,15 @@ u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
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}
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}
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u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
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u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed)
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u16 hw_led_mode, u32 chip_id)
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{
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{
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u8 port = params->port;
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u16 hw_led_mode = params->hw_led_mode;
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u8 rc = 0;
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u8 rc = 0;
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u32 tmp;
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u32 tmp;
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u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
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u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
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u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
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struct bnx2x *bp = params->bp;
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DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
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DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
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DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
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DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
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speed, hw_led_mode);
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speed, hw_led_mode);
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@ -5752,7 +5791,14 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
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break;
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break;
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case LED_MODE_OPER:
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case LED_MODE_OPER:
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REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
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if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
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REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
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REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
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} else {
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REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
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hw_led_mode);
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}
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REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
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REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
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port*4, 0);
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port*4, 0);
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/* Set blinking rate to ~15.9Hz */
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/* Set blinking rate to ~15.9Hz */
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@ -5764,7 +5810,7 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
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EMAC_WR(bp, EMAC_REG_EMAC_LED,
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EMAC_WR(bp, EMAC_REG_EMAC_LED,
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(tmp & (~EMAC_LED_OVERRIDE)));
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(tmp & (~EMAC_LED_OVERRIDE)));
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if (!CHIP_IS_E1H(bp) &&
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if (CHIP_IS_E1(bp) &&
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((speed == SPEED_2500) ||
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((speed == SPEED_2500) ||
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(speed == SPEED_1000) ||
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(speed == SPEED_1000) ||
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(speed == SPEED_100) ||
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(speed == SPEED_100) ||
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@ -6033,10 +6079,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
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REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
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REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
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params->port*4, 0);
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params->port*4, 0);
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bnx2x_set_led(bp, params->port, LED_MODE_OPER,
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bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed);
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vars->line_speed, params->hw_led_mode,
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params->chip_id);
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} else
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} else
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/* No loopback */
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/* No loopback */
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{
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{
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@ -6094,8 +6137,6 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
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{
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{
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struct bnx2x *bp = params->bp;
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struct bnx2x *bp = params->bp;
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u32 ext_phy_config = params->ext_phy_config;
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u32 ext_phy_config = params->ext_phy_config;
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u16 hw_led_mode = params->hw_led_mode;
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u32 chip_id = params->chip_id;
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u8 port = params->port;
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u8 port = params->port;
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u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
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u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
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u32 val = REG_RD(bp, params->shmem_base +
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u32 val = REG_RD(bp, params->shmem_base +
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@ -6130,7 +6171,7 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
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* Hold it as vars low
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* Hold it as vars low
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*/
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*/
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/* clear link led */
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/* clear link led */
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bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id);
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bnx2x_set_led(params, LED_MODE_OFF, 0);
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if (reset_ext_phy) {
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if (reset_ext_phy) {
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switch (ext_phy_type) {
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switch (ext_phy_type) {
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
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@ -6201,9 +6242,7 @@ static u8 bnx2x_update_link_down(struct link_params *params,
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u8 port = params->port;
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u8 port = params->port;
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DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
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DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
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bnx2x_set_led(bp, port, LED_MODE_OFF,
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bnx2x_set_led(params, LED_MODE_OFF, 0);
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0, params->hw_led_mode,
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params->chip_id);
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/* indicate no mac active */
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/* indicate no mac active */
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vars->mac_type = MAC_TYPE_NONE;
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vars->mac_type = MAC_TYPE_NONE;
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@ -6240,10 +6279,7 @@ static u8 bnx2x_update_link_up(struct link_params *params,
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vars->link_status |= LINK_STATUS_LINK_UP;
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vars->link_status |= LINK_STATUS_LINK_UP;
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if (link_10g) {
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if (link_10g) {
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bnx2x_bmac_enable(params, vars, 0);
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bnx2x_bmac_enable(params, vars, 0);
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bnx2x_set_led(bp, port, LED_MODE_OPER,
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bnx2x_set_led(params, LED_MODE_OPER, SPEED_10000);
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SPEED_10000, params->hw_led_mode,
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params->chip_id);
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} else {
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} else {
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bnx2x_emac_enable(params, vars, 0);
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bnx2x_emac_enable(params, vars, 0);
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rc = bnx2x_emac_program(params, vars->line_speed,
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rc = bnx2x_emac_program(params, vars->line_speed,
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@ -178,8 +178,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
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Basically, the CLC takes care of the led for the link, but in case one needs
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Basically, the CLC takes care of the led for the link, but in case one needs
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to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
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to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
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blink the led, and LED_MODE_OFF to set the led off.*/
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blink the led, and LED_MODE_OFF to set the led off.*/
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u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
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u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed);
|
||||||
u16 hw_led_mode, u32 chip_id);
|
|
||||||
#define LED_MODE_OFF 0
|
#define LED_MODE_OFF 0
|
||||||
#define LED_MODE_OPER 2
|
#define LED_MODE_OPER 2
|
||||||
|
|
||||||
|
|
|
@ -10855,7 +10855,6 @@ static void bnx2x_get_ethtool_stats(struct net_device *dev,
|
||||||
static int bnx2x_phys_id(struct net_device *dev, u32 data)
|
static int bnx2x_phys_id(struct net_device *dev, u32 data)
|
||||||
{
|
{
|
||||||
struct bnx2x *bp = netdev_priv(dev);
|
struct bnx2x *bp = netdev_priv(dev);
|
||||||
int port = BP_PORT(bp);
|
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if (!netif_running(dev))
|
if (!netif_running(dev))
|
||||||
|
@ -10869,13 +10868,10 @@ static int bnx2x_phys_id(struct net_device *dev, u32 data)
|
||||||
|
|
||||||
for (i = 0; i < (data * 2); i++) {
|
for (i = 0; i < (data * 2); i++) {
|
||||||
if ((i % 2) == 0)
|
if ((i % 2) == 0)
|
||||||
bnx2x_set_led(bp, port, LED_MODE_OPER, SPEED_1000,
|
bnx2x_set_led(&bp->link_params, LED_MODE_OPER,
|
||||||
bp->link_params.hw_led_mode,
|
SPEED_1000);
|
||||||
bp->link_params.chip_id);
|
|
||||||
else
|
else
|
||||||
bnx2x_set_led(bp, port, LED_MODE_OFF, 0,
|
bnx2x_set_led(&bp->link_params, LED_MODE_OFF, 0);
|
||||||
bp->link_params.hw_led_mode,
|
|
||||||
bp->link_params.chip_id);
|
|
||||||
|
|
||||||
msleep_interruptible(500);
|
msleep_interruptible(500);
|
||||||
if (signal_pending(current))
|
if (signal_pending(current))
|
||||||
|
@ -10883,10 +10879,8 @@ static int bnx2x_phys_id(struct net_device *dev, u32 data)
|
||||||
}
|
}
|
||||||
|
|
||||||
if (bp->link_vars.link_up)
|
if (bp->link_vars.link_up)
|
||||||
bnx2x_set_led(bp, port, LED_MODE_OPER,
|
bnx2x_set_led(&bp->link_params, LED_MODE_OPER,
|
||||||
bp->link_vars.line_speed,
|
bp->link_vars.line_speed);
|
||||||
bp->link_params.hw_led_mode,
|
|
||||||
bp->link_params.chip_id);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -4772,18 +4772,28 @@
|
||||||
#define PCI_ID_VAL2 0x438
|
#define PCI_ID_VAL2 0x438
|
||||||
|
|
||||||
|
|
||||||
#define MDIO_REG_BANK_CL73_IEEEB0 0x0
|
#define MDIO_REG_BANK_CL73_IEEEB0 0x0
|
||||||
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
|
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
|
||||||
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
|
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
|
||||||
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
|
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
|
||||||
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
|
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
|
||||||
|
|
||||||
#define MDIO_REG_BANK_CL73_IEEEB1 0x10
|
#define MDIO_REG_BANK_CL73_IEEEB1 0x10
|
||||||
#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
|
#define MDIO_CL73_IEEEB1_AN_ADV1 0x00
|
||||||
|
#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
|
||||||
|
#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
|
||||||
|
#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
|
||||||
|
#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
|
||||||
|
#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
|
||||||
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
|
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
|
||||||
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
|
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
|
||||||
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
|
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
|
||||||
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
|
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
|
||||||
|
#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
|
||||||
|
#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
|
||||||
|
#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
|
||||||
|
#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
|
||||||
|
#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
|
||||||
|
|
||||||
#define MDIO_REG_BANK_RX0 0x80b0
|
#define MDIO_REG_BANK_RX0 0x80b0
|
||||||
#define MDIO_RX0_RX_STATUS 0x10
|
#define MDIO_RX0_RX_STATUS 0x10
|
||||||
|
|
Loading…
Reference in a new issue