[MIPS] IP22: Get rid of volatile in IP22 core code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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2127435e57
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78709b9df3
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@ -52,8 +52,7 @@
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* national semiconductor nv ram chip the op code is 3 bits and
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* national semiconductor nv ram chip the op code is 3 bits and
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* the address is 6/8 bits.
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* the address is 6/8 bits.
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*/
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*/
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static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd,
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static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg)
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unsigned reg)
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{
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{
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unsigned short ser_cmd;
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unsigned short ser_cmd;
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int i;
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int i;
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@ -61,33 +60,34 @@ static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd,
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ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND));
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ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND));
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for (i = 0; i < BITS_IN_COMMAND; i++) {
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for (i = 0; i < BITS_IN_COMMAND; i++) {
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if (ser_cmd & (1<<15)) /* if high order bit set */
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if (ser_cmd & (1<<15)) /* if high order bit set */
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*ctrl |= EEPROM_DATO;
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writel(readl(ctrl) | EEPROM_DATO, ctrl);
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else
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else
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*ctrl &= ~EEPROM_DATO;
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writel(readl(ctrl) & ~EEPROM_DATO, ctrl);
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*ctrl &= ~EEPROM_ECLK;
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writel(readl(ctrl) & ~EEPROM_ECLK, ctrl);
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*ctrl |= EEPROM_ECLK;
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writel(readl(ctrl) | EEPROM_ECLK, ctrl);
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ser_cmd <<= 1;
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ser_cmd <<= 1;
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}
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}
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*ctrl &= ~EEPROM_DATO; /* see data sheet timing diagram */
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/* see data sheet timing diagram */
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writel(readl(ctrl) & ~EEPROM_DATO, ctrl);
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}
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}
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unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg)
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unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg)
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{
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{
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unsigned short res = 0;
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unsigned short res = 0;
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int i;
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int i;
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*ctrl &= ~EEPROM_EPROT;
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writel(readl(ctrl) & ~EEPROM_EPROT, ctrl);
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eeprom_cs_on(ctrl);
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eeprom_cs_on(ctrl);
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eeprom_cmd(ctrl, EEPROM_READ, reg);
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eeprom_cmd(ctrl, EEPROM_READ, reg);
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/* clock the data ouf of serial mem */
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/* clock the data ouf of serial mem */
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for (i = 0; i < 16; i++) {
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for (i = 0; i < 16; i++) {
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*ctrl &= ~EEPROM_ECLK;
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writel(readl(ctrl) & ~EEPROM_ECLK, ctrl);
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delay();
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delay();
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*ctrl |= EEPROM_ECLK;
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writel(readl(ctrl) | EEPROM_ECLK, ctrl);
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delay();
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delay();
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res <<= 1;
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res <<= 1;
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if (*ctrl & EEPROM_DATI)
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if (readl(ctrl) & EEPROM_DATI)
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res |= 1;
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res |= 1;
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}
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}
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@ -94,7 +94,7 @@ static int indy_rtc_set_time(unsigned long tim)
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static unsigned long dosample(void)
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static unsigned long dosample(void)
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{
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{
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u32 ct0, ct1;
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u32 ct0, ct1;
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volatile u8 msb, lsb;
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u8 msb, lsb;
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/* Start the counter. */
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/* Start the counter. */
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sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
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sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
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@ -107,21 +107,21 @@ static unsigned long dosample(void)
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/* Latch and spin until top byte of counter2 is zero */
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/* Latch and spin until top byte of counter2 is zero */
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do {
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do {
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sgint->tcword = SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT;
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writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword);
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lsb = sgint->tcnt2;
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lsb = readb(&sgint->tcnt2);
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msb = sgint->tcnt2;
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msb = readb(&sgint->tcnt2);
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ct1 = read_c0_count();
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ct1 = read_c0_count();
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} while (msb);
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} while (msb);
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/* Stop the counter. */
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/* Stop the counter. */
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sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
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writeb(sgint->tcword, (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
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SGINT_TCWORD_MSWST);
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SGINT_TCWORD_MSWST));
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/*
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/*
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* Return the difference, this is how far the r4k counter increments
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* Return the difference, this is how far the r4k counter increments
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* for every 1/HZ seconds. We round off the nearest 1 MHz of master
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* for every 1/HZ seconds. We round off the nearest 1 MHz of master
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* clock (= 1000000 / HZ / 2).
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* clock (= 1000000 / HZ / 2).
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*/
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*/
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/*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
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return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
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return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
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}
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}
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@ -206,7 +206,7 @@ struct hpc3_regs {
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#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
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#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
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#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
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#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
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volatile u32 eeprom; /* EEPROM data reg. */
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u32 eeprom; /* EEPROM data reg. */
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#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
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#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
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#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
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#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
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#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
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#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
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@ -72,7 +72,7 @@
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#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
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#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
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extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg);
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extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
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extern unsigned short ip22_nvram_read(int reg);
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extern unsigned short ip22_nvram_read(int reg);
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#endif
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#endif
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@ -57,7 +57,7 @@ struct sgimc_regs {
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volatile u32 divider; /* Divider reg for RPSS */
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volatile u32 divider; /* Divider reg for RPSS */
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u32 _unused5;
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u32 _unused5;
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volatile u32 eeprom; /* EEPROM byte reg for r4k */
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u32 eeprom; /* EEPROM byte reg for r4k */
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#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
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#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
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#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
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#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
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#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
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#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
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