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[ARM] Remove RETINSTR macro 

RETINSTR is a left-over from the days when we had 26-bit and
32-bit CPU support integrated into the same tree.  Since this
is no longer the case, we can now remove RETINSTR.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
wifi-calibration
Russell King 2006-06-25 11:17:23 +01:00 committed by Russell King
parent dfd8317d33
commit 7999d8d7a6
11 changed files with 22 additions and 28 deletions
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2
arch/arm/kernel/entry-common.S
View File

@ -340,7 +340,7 @@ sys_mmap2:
streq r5, [sp, #4]
beq do_mmap2
mov r0, #-EINVAL
RETINSTR(mov,pc, lr)
mov pc, lr
#else
str r5, [sp, #4]
b do_mmap2

18
arch/arm/lib/delay.S
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@ -31,7 +31,7 @@ ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06
mov r2, r2, lsr #10 @ max = 0x00007fff
mul r0, r2, r0 @ max = 2^32-1
movs r0, r0, lsr #6
RETINSTR(moveq,pc,lr)
moveq pc, lr
/*
* loops = r0 * HZ * loops_per_jiffy / 1000000
@ -43,20 +43,20 @@ ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06
ENTRY(__delay)
subs r0, r0, #1
#if 0
RETINSTR(movls,pc,lr)
movls pc, lr
subs r0, r0, #1
RETINSTR(movls,pc,lr)
movls pc, lr
subs r0, r0, #1
RETINSTR(movls,pc,lr)
movls pc, lr
subs r0, r0, #1
RETINSTR(movls,pc,lr)
movls pc, lr
subs r0, r0, #1
RETINSTR(movls,pc,lr)
movls pc, lr
subs r0, r0, #1
RETINSTR(movls,pc,lr)
movls pc, lr
subs r0, r0, #1
RETINSTR(movls,pc,lr)
movls pc, lr
subs r0, r0, #1
#endif
bhi __delay
RETINSTR(mov,pc,lr)
mov pc, lr

10
arch/arm/lib/findbit.S
View File

@ -32,7 +32,7 @@ ENTRY(_find_first_zero_bit_le)
2: cmp r2, r1 @ any more?
blo 1b
3: mov r0, r1 @ no free bits
RETINSTR(mov,pc,lr)
mov pc, lr
/*
* Purpose : Find next 'zero' bit
@ -66,7 +66,7 @@ ENTRY(_find_first_bit_le)
2: cmp r2, r1 @ any more?
blo 1b
3: mov r0, r1 @ no free bits
RETINSTR(mov,pc,lr)
mov pc, lr
/*
* Purpose : Find next 'one' bit
@ -98,7 +98,7 @@ ENTRY(_find_first_zero_bit_be)
2: cmp r2, r1 @ any more?
blo 1b
3: mov r0, r1 @ no free bits
RETINSTR(mov,pc,lr)
mov pc, lr
ENTRY(_find_next_zero_bit_be)
teq r1, #0
@ -126,7 +126,7 @@ ENTRY(_find_first_bit_be)
2: cmp r2, r1 @ any more?
blo 1b
3: mov r0, r1 @ no free bits
RETINSTR(mov,pc,lr)
mov pc, lr
ENTRY(_find_next_bit_be)
teq r1, #0
@ -164,5 +164,5 @@ ENTRY(_find_next_bit_be)
addeq r2, r2, #1
mov r0, r2
#endif
RETINSTR(mov,pc,lr)
mov pc, lr

2
arch/arm/lib/io-readsw-armv3.S
View File

@ -28,7 +28,7 @@
strb r3, [r1], #1
subs r2, r2, #1
RETINSTR(moveq, pc, lr)
moveq pc, lr
ENTRY(__raw_readsw)
teq r2, #0 @ do we have to check for the zero len?

2
arch/arm/lib/io-writesw-armv3.S
View File

@ -29,7 +29,7 @@
orr r3, r3, r3, lsl #16
str r3, [r0]
subs r2, r2, #1
RETINSTR(moveq, pc, lr)
moveq pc, lr
ENTRY(__raw_writesw)
teq r2, #0 @ do we have to check for the zero len?

2
arch/arm/lib/memchr.S
View File

@ -22,4 +22,4 @@ ENTRY(memchr)
bne 1b
sub r0, r0, #1
2: movne r0, #0
RETINSTR(mov,pc,lr)
mov pc, lr

2
arch/arm/lib/memset.S
View File

@ -77,4 +77,4 @@ ENTRY(memset)
strneb r1, [r0], #1
tst r2, #1
strneb r1, [r0], #1
RETINSTR(mov,pc,lr)
mov pc, lr

2
arch/arm/lib/memzero.S
View File

@ -77,4 +77,4 @@ ENTRY(__memzero)
strneb r2, [r0], #1 @ 1
tst r1, #1 @ 1 a byte left over
strneb r2, [r0], #1 @ 1
RETINSTR(mov,pc,lr) @ 1
mov pc, lr @ 1

2
arch/arm/lib/strchr.S
View File

@ -23,4 +23,4 @@ ENTRY(strchr)
teq r2, r1
movne r0, #0
subeq r0, r0, #1
RETINSTR(mov,pc,lr)
mov pc, lr

2
arch/arm/lib/strrchr.S
View File

@ -22,4 +22,4 @@ ENTRY(strrchr)
teq r2, #0
bne 1b
mov r0, r3
RETINSTR(mov,pc,lr)
mov pc, lr

6
include/asm-arm/assembler.h
View File

@ -73,12 +73,6 @@
ldm/**/cond base,reglist
#endif
/*
* Build a return instruction for this processor type.
*/
#define RETINSTR(instr, regs...)\
instr regs
/*
* Enable and disable interrupts
*/