[ARM] Remove RETINSTR macro
RETINSTR is a left-over from the days when we had 26-bit and 32-bit CPU support integrated into the same tree. Since this is no longer the case, we can now remove RETINSTR. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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dfd8317d33
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@ -340,7 +340,7 @@ sys_mmap2:
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streq r5, [sp, #4]
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beq do_mmap2
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mov r0, #-EINVAL
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RETINSTR(mov,pc, lr)
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mov pc, lr
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#else
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str r5, [sp, #4]
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b do_mmap2
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@ -31,7 +31,7 @@ ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06
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mov r2, r2, lsr #10 @ max = 0x00007fff
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mul r0, r2, r0 @ max = 2^32-1
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movs r0, r0, lsr #6
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RETINSTR(moveq,pc,lr)
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moveq pc, lr
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/*
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* loops = r0 * HZ * loops_per_jiffy / 1000000
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@ -43,20 +43,20 @@ ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06
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ENTRY(__delay)
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subs r0, r0, #1
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#if 0
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RETINSTR(movls,pc,lr)
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movls pc, lr
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subs r0, r0, #1
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RETINSTR(movls,pc,lr)
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movls pc, lr
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subs r0, r0, #1
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RETINSTR(movls,pc,lr)
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movls pc, lr
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subs r0, r0, #1
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RETINSTR(movls,pc,lr)
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movls pc, lr
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subs r0, r0, #1
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RETINSTR(movls,pc,lr)
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movls pc, lr
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subs r0, r0, #1
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RETINSTR(movls,pc,lr)
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movls pc, lr
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subs r0, r0, #1
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RETINSTR(movls,pc,lr)
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movls pc, lr
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subs r0, r0, #1
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#endif
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bhi __delay
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RETINSTR(mov,pc,lr)
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mov pc, lr
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@ -32,7 +32,7 @@ ENTRY(_find_first_zero_bit_le)
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2: cmp r2, r1 @ any more?
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blo 1b
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3: mov r0, r1 @ no free bits
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RETINSTR(mov,pc,lr)
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mov pc, lr
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/*
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* Purpose : Find next 'zero' bit
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@ -66,7 +66,7 @@ ENTRY(_find_first_bit_le)
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2: cmp r2, r1 @ any more?
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blo 1b
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3: mov r0, r1 @ no free bits
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RETINSTR(mov,pc,lr)
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mov pc, lr
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/*
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* Purpose : Find next 'one' bit
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@ -98,7 +98,7 @@ ENTRY(_find_first_zero_bit_be)
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2: cmp r2, r1 @ any more?
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blo 1b
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3: mov r0, r1 @ no free bits
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RETINSTR(mov,pc,lr)
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mov pc, lr
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ENTRY(_find_next_zero_bit_be)
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teq r1, #0
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@ -126,7 +126,7 @@ ENTRY(_find_first_bit_be)
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2: cmp r2, r1 @ any more?
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blo 1b
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3: mov r0, r1 @ no free bits
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RETINSTR(mov,pc,lr)
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mov pc, lr
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ENTRY(_find_next_bit_be)
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teq r1, #0
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@ -164,5 +164,5 @@ ENTRY(_find_next_bit_be)
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addeq r2, r2, #1
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mov r0, r2
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#endif
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RETINSTR(mov,pc,lr)
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mov pc, lr
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@ -28,7 +28,7 @@
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strb r3, [r1], #1
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subs r2, r2, #1
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RETINSTR(moveq, pc, lr)
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moveq pc, lr
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ENTRY(__raw_readsw)
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teq r2, #0 @ do we have to check for the zero len?
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@ -29,7 +29,7 @@
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orr r3, r3, r3, lsl #16
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str r3, [r0]
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subs r2, r2, #1
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RETINSTR(moveq, pc, lr)
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moveq pc, lr
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ENTRY(__raw_writesw)
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teq r2, #0 @ do we have to check for the zero len?
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@ -22,4 +22,4 @@ ENTRY(memchr)
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bne 1b
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sub r0, r0, #1
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2: movne r0, #0
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RETINSTR(mov,pc,lr)
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mov pc, lr
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@ -77,4 +77,4 @@ ENTRY(memset)
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strneb r1, [r0], #1
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tst r2, #1
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strneb r1, [r0], #1
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RETINSTR(mov,pc,lr)
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mov pc, lr
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@ -77,4 +77,4 @@ ENTRY(__memzero)
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strneb r2, [r0], #1 @ 1
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tst r1, #1 @ 1 a byte left over
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strneb r2, [r0], #1 @ 1
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RETINSTR(mov,pc,lr) @ 1
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mov pc, lr @ 1
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@ -23,4 +23,4 @@ ENTRY(strchr)
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teq r2, r1
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movne r0, #0
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subeq r0, r0, #1
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RETINSTR(mov,pc,lr)
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mov pc, lr
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@ -22,4 +22,4 @@ ENTRY(strrchr)
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teq r2, #0
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bne 1b
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mov r0, r3
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RETINSTR(mov,pc,lr)
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mov pc, lr
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@ -73,12 +73,6 @@
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ldm/**/cond base,reglist
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#endif
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/*
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* Build a return instruction for this processor type.
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*/
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#define RETINSTR(instr, regs...)\
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instr regs
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/*
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* Enable and disable interrupts
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*/
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