x86, suspend: Restore MISC_ENABLE MSR in realmode wakeup
Some BIOSes will reset the Intel MISC_ENABLE MSR (specifically the
XD_DISABLE bit) when resuming from S3, which can interact poorly with
ebba638ae7
. In 32bit PAE mode, this can
lead to a fault when EFER is restored by the kernel wakeup routines,
due to it setting the NX bit for a CPU that (thanks to the BIOS reset)
now incorrectly thinks it lacks the NX feature. (64bit is not affected
because it uses a common CPU bring-up that specifically handles the
XD_DISABLE bit.)
The need for MISC_ENABLE being restored so early is specific to the S3
resume path. Normally, MISC_ENABLE is saved in save_processor_state(),
but this happens after the resume header is created, so just reproduce
the logic here. (acpi_suspend_lowlevel() creates the header, calls
do_suspend_lowlevel, which calls save_processor_state(), so the saved
processor context isn't available during resume header creation.)
[ hpa: Consider for stable if OK in mainline ]
Signed-off-by: Kees Cook <kees.cook@canonical.com>
Link: http://lkml.kernel.org/r/20110707011034.GA8523@outflux.net
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: <stable@kernel.org> 2.6.38+
This commit is contained in:
parent
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@ -28,6 +28,8 @@ pmode_cr3: .long 0 /* Saved %cr3 */
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pmode_cr4: .long 0 /* Saved %cr4 */
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pmode_efer: .quad 0 /* Saved EFER */
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pmode_gdt: .quad 0
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pmode_misc_en: .quad 0 /* Saved MISC_ENABLE MSR */
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pmode_behavior: .long 0 /* Wakeup behavior flags */
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realmode_flags: .long 0
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real_magic: .long 0
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trampoline_segment: .word 0
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@ -91,6 +93,18 @@ wakeup_code:
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/* Call the C code */
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calll main
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/* Restore MISC_ENABLE before entering protected mode, in case
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BIOS decided to clear XD_DISABLE during S3. */
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movl pmode_behavior, %eax
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btl $WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE, %eax
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jnc 1f
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movl pmode_misc_en, %eax
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movl pmode_misc_en + 4, %edx
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movl $MSR_IA32_MISC_ENABLE, %ecx
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wrmsr
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1:
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/* Do any other stuff... */
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#ifndef CONFIG_64BIT
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@ -21,6 +21,9 @@ struct wakeup_header {
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u32 pmode_efer_low; /* Protected mode EFER */
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u32 pmode_efer_high;
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u64 pmode_gdt;
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u32 pmode_misc_en_low; /* Protected mode MISC_ENABLE */
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u32 pmode_misc_en_high;
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u32 pmode_behavior; /* Wakeup routine behavior flags */
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u32 realmode_flags;
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u32 real_magic;
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u16 trampoline_segment; /* segment with trampoline code, 64-bit only */
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@ -39,4 +42,7 @@ extern struct wakeup_header wakeup_header;
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#define WAKEUP_HEADER_SIGNATURE 0x51ee1111
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#define WAKEUP_END_SIGNATURE 0x65a22c82
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/* Wakeup behavior bits */
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#define WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE 0
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#endif /* ARCH_X86_KERNEL_ACPI_RM_WAKEUP_H */
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@ -77,6 +77,12 @@ int acpi_suspend_lowlevel(void)
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header->pmode_cr0 = read_cr0();
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header->pmode_cr4 = read_cr4_safe();
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header->pmode_behavior = 0;
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if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
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&header->pmode_misc_en_low,
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&header->pmode_misc_en_high))
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header->pmode_behavior |=
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(1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE);
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header->realmode_flags = acpi_realmode_flags;
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header->real_magic = 0x12345678;
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