ARM: dts: qcom: Add apq8064 CoreSight components
Add initial set of CoreSight components found on Qualcomm apq8064 based platforms, including the IFC6410 board. Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org> Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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@ -4,6 +4,7 @@
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#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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#include <dt-bindings/reset/qcom,gcc-msm8960.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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@ -32,7 +33,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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CPU0: cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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@ -43,7 +44,7 @@
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@1 {
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CPU1: cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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@ -54,7 +55,7 @@
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@2 {
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CPU2: cpu@2 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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@ -65,7 +66,7 @@
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@3 {
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CPU3: cpu@3 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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@ -1512,6 +1513,187 @@
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};
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};
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};
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etb@1a01000 {
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compatible = "coresight-etb10", "arm,primecell";
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reg = <0x1a01000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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port {
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etb_in: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out0>;
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};
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};
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};
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tpiu@1a03000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0x1a03000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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port {
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tpiu_in: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out1>;
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};
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};
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};
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replicator {
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compatible = "arm,coresight-replicator";
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator_out0: endpoint {
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remote-endpoint = <&etb_in>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out1: endpoint {
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remote-endpoint = <&tpiu_in>;
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};
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};
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port@2 {
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reg = <0>;
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replicator_in: endpoint {
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slave-mode;
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remote-endpoint = <&funnel_out>;
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};
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};
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};
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};
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funnel@1a04000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0x1a04000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* Not described input ports:
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* 2 - connected to STM component
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* 3 - not-connected
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* 6 - not-connected
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* 7 - not-connected
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*/
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port@0 {
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reg = <0>;
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funnel_in0: endpoint {
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slave-mode;
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remote-endpoint = <&etm0_out>;
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};
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};
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port@1 {
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reg = <1>;
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funnel_in1: endpoint {
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slave-mode;
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remote-endpoint = <&etm1_out>;
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};
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};
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port@4 {
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reg = <4>;
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funnel_in4: endpoint {
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slave-mode;
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remote-endpoint = <&etm2_out>;
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};
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};
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port@5 {
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reg = <5>;
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funnel_in5: endpoint {
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slave-mode;
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remote-endpoint = <&etm3_out>;
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};
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};
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port@8 {
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reg = <0>;
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funnel_out: endpoint {
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remote-endpoint = <&replicator_in>;
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};
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};
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};
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};
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etm@1a1c000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x1a1c000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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cpu = <&CPU0>;
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port {
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etm0_out: endpoint {
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remote-endpoint = <&funnel_in0>;
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};
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};
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};
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etm@1a1d000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x1a1d000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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cpu = <&CPU1>;
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port {
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etm1_out: endpoint {
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remote-endpoint = <&funnel_in1>;
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};
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};
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};
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etm@1a1e000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x1a1e000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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cpu = <&CPU2>;
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port {
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etm2_out: endpoint {
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remote-endpoint = <&funnel_in4>;
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};
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};
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};
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etm@1a1f000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0x1a1f000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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clock-names = "apb_pclk";
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cpu = <&CPU3>;
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port {
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etm3_out: endpoint {
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remote-endpoint = <&funnel_in5>;
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};
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};
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};
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};
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};
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#include "qcom-apq8064-pins.dtsi"
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