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ux500 GPIO and pinctrl changes for kernel 3.5

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-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABAgAGBQJPrioxAAoJEEEQszewGV1zpPkP/1nMK0LMo8sy7ScnCCumNils
 ZiWgB8pViyfl5gLggOwldI/ILVzXTbR6pJZAJNoU3Tbu7n96UyA2QCdeBn/JKCbY
 Yr0I/8uT0hXlh4QVrCgyVKQt2e05rP2mt8vtP1CoFad0R56RfwZ9U9u9S2kx5DnY
 oKXeg/sjxURueMPYQuvZVZBdLJ+82rsBNVXukKb2h2gY8ntMm6CBLUgk/oHBpPrM
 CWaNBT0llBwwWhsmrErYZ7Sb7nRRGDL2rf6kKrw1UPwZ5FIefS+RHaudRic/AiGD
 DfVGh22hpv0WFQ6ruEayA1JfoYS0IKsvGBn8Ywf+2tz9uteED6rXJ+fOF6FayR6y
 NarGmCFUoQauh5ZSK8h7nv0oNlRFgb3OFp/FfLZC9N+jCWJVVbtbLD9X+M5wN6aE
 lUjQwVbiA7q7ZTYs12X/zzBjrQj+ZrV5IXZLq+dvZ1HKBh4FLSpXaZocOCP0n0f1
 N4VkGgIngWeiQDDJqc11mZ3ueD/p2AsWsxLRAEafL5CaIk+vz9JXcF3gYDt57Oph
 WjPOWXTHiRxb1W4OfgvKWtZbxJdqECJ8HnWUbpTjiG0/MK8Tfprk8iSEOqS2tM1B
 usBXBLk8I4P2RwGgIcsnuJ1gEEsZzjSbvpxf2VKVvdP86qw7LizYrEjXKvjnq4G/
 nGSTZ3F3/53x2mFEihpM
 =xjdL
 -----END PGP SIGNATURE-----

Merge tag 'ux500-gpio-pins-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/pinctrl

ux500 GPIO and pinctrl changes for kernel 3.5

* tag 'ux500-gpio-pins-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
  ARM: ux500: switch MSP to using pinctrl for pins
  ARM: ux500: alter MSP registration to return a device pointer
  ARM: ux500: switch to using pinctrl for uart0
  ARM: ux500: delete custom pin control system
  ARM: ux500: switch over to Nomadik pinctrl driver
  pinctrl: add sleep state definition
  pinctrl/nomadik: implement pin configuration
  pinctrl/nomadik: implement pin multiplexing
  pinctrl/nomadik: reuse GPIO debug function for pins
  pinctrl/nomadik: break out single GPIO debug function
  pinctrl/nomadik: basic Nomadik pinctrl interface
  pinctrl/nomadik: !CONFIG_OF build error
  gpio: move the Nomadik GPIO driver to pinctrl

Context conflicts resolved in drivers/pinctrl/Kconfig and
drivers/pinctrl/Makefile.

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2012-05-12 19:57:34 -07:00
parent 7afeca1a30 08d98fe0e8
commit 7af07ad902
18 changed files with 2054 additions and 680 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
arch/arm/mach-ux500/Kconfig
View file

@ -9,6 +9,8 @@ config UX500_SOC_COMMON
select ARM_ERRATA_754322
select ARM_ERRATA_764369
select CACHE_L2X0
select PINCTRL
select PINCTRL_NOMADIK
config UX500_SOC_DB5500
bool
@ -20,6 +22,7 @@ config UX500_SOC_DB8500
select REGULATOR
select REGULATOR_DB8500_PRCMU
select CPU_FREQ_TABLE if CPU_FREQ
select PINCTRL_DB8500
menu "Ux500 target platform (boards)"

2
arch/arm/mach-ux500/Makefile
View file

@ -3,7 +3,7 @@
#
obj-y := clock.o cpu.o devices.o devices-common.o \
id.o pins.o usb.o timer.o
id.o usb.o timer.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o
obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o

85
arch/arm/mach-ux500/board-mop500-msp.c
View file

@ -7,17 +7,18 @@
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <plat/gpio-nomadik.h>
#include <linux/pinctrl/consumer.h>
#include <plat/gpio-nomadik.h>
#include <plat/pincfg.h>
#include <plat/ste_dma40.h>
#include <mach/devices.h>
#include <ste-dma40-db8500.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/msp.h>
#include "ste-dma40-db8500.h"
#include "board-mop500.h"
#include "devices-db8500.h"
#include "pins-db8500.h"
@ -28,19 +29,10 @@ static DEFINE_SPINLOCK(msp_rxtx_lock);
/* Reference Count */
static int msp_rxtx_ref;
static pin_cfg_t mop500_msp1_pins_init[] = {
GPIO33_MSP1_TXD | PIN_OUTPUT_LOW | PIN_SLPM_WAKEUP_DISABLE,
GPIO34_MSP1_TFS | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_DISABLE,
GPIO35_MSP1_TCK | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_DISABLE,
GPIO36_MSP1_RXD | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_DISABLE,
};
static pin_cfg_t mop500_msp1_pins_exit[] = {
GPIO33_MSP1_TXD | PIN_OUTPUT_LOW | PIN_SLPM_WAKEUP_ENABLE,
GPIO34_MSP1_TFS | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_ENABLE,
GPIO35_MSP1_TCK | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_ENABLE,
GPIO36_MSP1_RXD | PIN_INPUT_NOPULL | PIN_SLPM_WAKEUP_ENABLE,
};
/* Pin modes */
struct pinctrl *msp1_p;
struct pinctrl_state *msp1_def;
struct pinctrl_state *msp1_sleep;
int msp13_i2s_init(void)
{
@ -48,9 +40,11 @@ int msp13_i2s_init(void)
unsigned long flags;
spin_lock_irqsave(&msp_rxtx_lock, flags);
if (msp_rxtx_ref == 0)
retval = nmk_config_pins(
ARRAY_AND_SIZE(mop500_msp1_pins_init));
if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
retval = pinctrl_select_state(msp1_p, msp1_def);
if (retval)
pr_err("could not set MSP1 defstate\n");
}
if (!retval)
msp_rxtx_ref++;
spin_unlock_irqrestore(&msp_rxtx_lock, flags);
@ -66,9 +60,11 @@ int msp13_i2s_exit(void)
spin_lock_irqsave(&msp_rxtx_lock, flags);
WARN_ON(!msp_rxtx_ref);
msp_rxtx_ref--;
if (msp_rxtx_ref == 0)
retval = nmk_config_pins_sleep(
ARRAY_AND_SIZE(mop500_msp1_pins_exit));
if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
retval = pinctrl_select_state(msp1_p, msp1_sleep);
if (retval)
pr_err("could not set MSP1 sleepstate\n");
}
spin_unlock_irqrestore(&msp_rxtx_lock, flags);
return retval;
@ -170,7 +166,8 @@ static struct stedma40_chan_cfg msp2_dma_tx = {
/* data_width is set during configuration */
};
static int db8500_add_msp_i2s(struct device *parent, int id,
static struct platform_device *db8500_add_msp_i2s(struct device *parent,
int id,
resource_size_t base, int irq,
struct msp_i2s_platform_data *pdata)
{
@ -188,10 +185,10 @@ static int db8500_add_msp_i2s(struct device *parent, int id,
if (!pdev) {
pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
id);
return -EIO;
return NULL;
}
return 0;
return pdev;
}
/* Platform device for ASoC U8500 machine */
@ -228,23 +225,43 @@ static struct msp_i2s_platform_data msp3_platform_data = {
int mop500_msp_init(struct device *parent)
{
int ret;
struct platform_device *msp1;
pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
platform_device_register(&snd_soc_u8500);
pr_info("Initialize MSP I2S-devices.\n");
ret = db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
&msp0_platform_data);
ret |= db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
&msp1_platform_data);
ret |= db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
&msp2_platform_data);
ret |= db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
&msp3_platform_data);
db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
&msp0_platform_data);
msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
&msp1_platform_data);
db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
&msp2_platform_data);
db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
&msp3_platform_data);
/* Get the pinctrl handle for MSP1 */
if (msp1) {
msp1_p = pinctrl_get(&msp1->dev);
if (IS_ERR(msp1_p))
dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
else {
msp1_def = pinctrl_lookup_state(msp1_p,
PINCTRL_STATE_DEFAULT);
if (IS_ERR(msp1_def)) {
dev_err(&msp1->dev,
"could not get MSP1 defstate\n");
}
msp1_sleep = pinctrl_lookup_state(msp1_p,
PINCTRL_STATE_SLEEP);
if (IS_ERR(msp1_sleep))
dev_err(&msp1->dev,
"could not get MSP1 idlestate\n");
}
}
pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
platform_device_register(&ux500_pcm);
return ret;
return 0;
}

871
arch/arm/mach-ux500/board-mop500-pins.c
View file

@ -8,6 +8,7 @@
#include <linux/init.h>
#include <linux/bug.h>
#include <linux/string.h>
#include <linux/pinctrl/machine.h>
#include <asm/mach-types.h>
#include <plat/pincfg.h>
@ -16,7 +17,6 @@
#include <mach/hardware.h>
#include "pins-db8500.h"
#include "pins.h"
#include "board-mop500.h"
enum custom_pin_cfg_t {
@ -26,399 +26,425 @@ enum custom_pin_cfg_t {
static enum custom_pin_cfg_t pinsfor;
static pin_cfg_t mop500_pins_common[] = {
/* uMSP0 */
GPIO12_MSP0_TXD,
GPIO13_MSP0_TFS,
GPIO14_MSP0_TCK,
GPIO15_MSP0_RXD,
/* These simply sets bias for pins */
#define BIAS(a,b) static unsigned long a[] = { b }
/* MSP2: HDMI */
GPIO193_MSP2_TXD | PIN_INPUT_PULLDOWN,
GPIO194_MSP2_TCK | PIN_INPUT_PULLDOWN,
GPIO195_MSP2_TFS | PIN_INPUT_PULLDOWN,
GPIO196_MSP2_RXD | PIN_OUTPUT_LOW,
BIAS(pd, PIN_PULL_DOWN);
BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
BIAS(in_nopull, PIN_INPUT_NOPULL);
BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
BIAS(in_pu, PIN_INPUT_PULLUP);
BIAS(in_pd, PIN_INPUT_PULLDOWN);
BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
BIAS(out_hi, PIN_OUTPUT_HIGH);
BIAS(out_lo, PIN_OUTPUT_LOW);
BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
/* These also force them into GPIO mode */
BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
/* Sleep modes */
BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
/* LCD TE0 */
GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP,
/* We use these to define hog settings that are always done on boot */
#define DB8500_MUX_HOG(group,func) \
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
#define DB8500_PIN_HOG(pin,conf) \
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
/* Touch screen INTERFACE */
GPIO84_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT1 */
/* These are default states associated with device and changed runtime */
#define DB8500_MUX(group,func,dev) \
PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
#define DB8500_PIN(pin,conf,dev) \
PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
/* STMPE1601/tc35893 keypad IRQ */
GPIO218_GPIO | PIN_INPUT_PULLUP,
#define DB8500_PIN_SLEEP(pin,conf,dev) \
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
pin, conf)
/* UART */
/* uart-0 pins gpio configuration should be
* kept intact to prevent glitch in tx line
* when tty dev is opened. Later these pins
* are configured to uart mop500_pins_uart0
*
* It will be replaced with uart configuration
* once the issue is solved.
/* Pin control settings */
static struct pinctrl_map __initdata mop500_family_pinmap[] = {
/*
* uMSP0, mux in 4 pins, regular placement of RX/TX
* explicitly set the pins to no pull
*/
GPIO0_GPIO | PIN_INPUT_PULLUP,
GPIO1_GPIO | PIN_OUTPUT_HIGH,
GPIO2_GPIO | PIN_INPUT_PULLUP,
GPIO3_GPIO | PIN_OUTPUT_HIGH,
GPIO29_U2_RXD | PIN_INPUT_PULLUP,
GPIO30_U2_TXD | PIN_OUTPUT_HIGH,
GPIO31_U2_CTSn | PIN_INPUT_PULLUP,
GPIO32_U2_RTSn | PIN_OUTPUT_HIGH,
};
static pin_cfg_t mop500_pins_default[] = {
/* SSP0 */
GPIO143_SSP0_CLK,
GPIO144_SSP0_FRM,
GPIO145_SSP0_RXD | PIN_PULL_DOWN,
GPIO146_SSP0_TXD,
/* XENON Flashgun INTERFACE */
GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */
GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */
GPIO217_GPIO | PIN_INPUT_PULLUP, /* TC35892 IRQ */
/* sdi0 (removable MMC/SD/SDIO cards) not handled by pm_runtime */
GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
/* UART */
GPIO4_U1_RXD | PIN_INPUT_PULLUP,
GPIO5_U1_TXD | PIN_OUTPUT_HIGH,
GPIO6_U1_CTSn | PIN_INPUT_PULLUP,
GPIO7_U1_RTSn | PIN_OUTPUT_HIGH,
};
static pin_cfg_t hrefv60_pins[] = {
/* WLAN */
GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */
/* XENON Flashgun INTERFACE */
GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */
GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */
/* Assistant LED INTERFACE */
GPIO21_GPIO | PIN_OUTPUT_LOW, /* XENON_EN1 */
GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW, /* XENON_EN2 */
/* Magnetometer */
GPIO31_GPIO | PIN_INPUT_PULLUP, /* magnetometer_INT */
GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */
/* Display Interface */
GPIO65_GPIO | PIN_OUTPUT_HIGH, /* DISP1 NO RST */
GPIO66_GPIO | PIN_OUTPUT_LOW, /* DISP2 RST */
/* Touch screen INTERFACE */
GPIO143_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST1 */
/* Touch screen INTERFACE 2 */
GPIO67_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT2 */
GPIO146_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST2 */
/* ETM_PTM_TRACE INTERFACE */
GPIO70_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */
GPIO71_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */
GPIO72_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */
GPIO73_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */
GPIO74_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */
/* NAHJ INTERFACE */
GPIO76_GPIO | PIN_OUTPUT_LOW,/* NAHJ_CTRL */
GPIO216_GPIO | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */
/* NFC INTERFACE */
GPIO77_GPIO | PIN_OUTPUT_LOW, /* NFC_ENA */
GPIO144_GPIO | PIN_INPUT_PULLDOWN, /* NFC_IRQ */
GPIO142_GPIO | PIN_OUTPUT_LOW, /* NFC_RESET */
/* Keyboard MATRIX INTERFACE */
GPIO90_MC5_CMD | PIN_OUTPUT_LOW, /* KP_O_1 */
GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */
GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */
GPIO96_KP_O6 | PIN_OUTPUT_LOW, /* KP_O_6 */
GPIO94_KP_O7 | PIN_OUTPUT_LOW, /* KP_O_7 */
GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */
GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */
GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */
GPIO91_GPIO | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */
GPIO92_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */
GPIO97_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */
/* DiPro Sensor Interface */
GPIO139_GPIO | PIN_INPUT_PULLUP, /* DIPRO_INT */
/* Audio Amplifier Interface */
GPIO149_GPIO | PIN_OUTPUT_HIGH, /* VAUDIO_HF_EN, enable MAX8968 */
/* GBF INTERFACE */
GPIO171_GPIO | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */
/* MSP : HDTV INTERFACE */
GPIO192_GPIO | PIN_INPUT_PULLDOWN,
/* ACCELEROMETER_INTERFACE */
GPIO82_GPIO | PIN_INPUT_PULLUP, /* ACC_INT1 */
GPIO83_GPIO | PIN_INPUT_PULLUP, /* ACC_INT2 */
/* SD card detect */
GPIO95_GPIO | PIN_INPUT_PULLUP,
};
static pin_cfg_t u9500_pins[] = {
GPIO4_U1_RXD | PIN_INPUT_PULLUP,
GPIO5_U1_TXD | PIN_OUTPUT_HIGH,
GPIO144_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */
/* HSI */
GPIO219_HSIR_FLA0 | PIN_INPUT_PULLDOWN,
GPIO220_HSIR_DAT0 | PIN_INPUT_PULLDOWN,
GPIO221_HSIR_RDY0 | PIN_OUTPUT_LOW,
GPIO222_HSIT_FLA0 | PIN_OUTPUT_LOW,
GPIO223_HSIT_DAT0 | PIN_OUTPUT_LOW,
GPIO224_HSIT_RDY0 | PIN_INPUT_PULLDOWN,
GPIO225_HSIT_CAWAKE0 | PIN_INPUT_PULLDOWN, /* CA_WAKE0 */
GPIO226_GPIO | PIN_OUTPUT_HIGH, /* AC_WAKE0 */
};
static pin_cfg_t u8500_pins[] = {
GPIO226_GPIO | PIN_OUTPUT_LOW, /* WLAN_PMU_EN */
GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */
};
static pin_cfg_t snowball_pins[] = {
/* SSP0, to AB8500 */
GPIO143_SSP0_CLK,
GPIO144_SSP0_FRM,
GPIO145_SSP0_RXD | PIN_PULL_DOWN,
GPIO146_SSP0_TXD,
/* MMC0: MicroSD card */
GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
/* MMC2: LAN */
GPIO86_SM_ADQ0,
GPIO87_SM_ADQ1,
GPIO88_SM_ADQ2,
GPIO89_SM_ADQ3,
GPIO90_SM_ADQ4,
GPIO91_SM_ADQ5,
GPIO92_SM_ADQ6,
GPIO93_SM_ADQ7,
GPIO94_SM_ADVn,
GPIO95_SM_CS0n,
GPIO96_SM_OEn,
GPIO97_SM_WEn,
GPIO128_SM_CKO,
GPIO130_SM_FBCLK,
GPIO131_SM_ADQ8,
GPIO132_SM_ADQ9,
GPIO133_SM_ADQ10,
GPIO134_SM_ADQ11,
GPIO135_SM_ADQ12,
GPIO136_SM_ADQ13,
GPIO137_SM_ADQ14,
GPIO138_SM_ADQ15,
/* RSTn_LAN */
GPIO141_GPIO | PIN_OUTPUT_HIGH,
/* Accelerometer/Magnetometer */
GPIO163_GPIO | PIN_INPUT_PULLUP, /* ACCEL_IRQ1 */
GPIO164_GPIO | PIN_INPUT_PULLUP, /* ACCEL_IRQ2 */
GPIO165_GPIO | PIN_INPUT_PULLUP, /* MAG_DRDY */
/* WLAN/GBF */
GPIO161_GPIO | PIN_OUTPUT_LOW, /* WLAN_PMU_EN */
GPIO171_GPIO | PIN_OUTPUT_HIGH,/* GBF_ENA */
GPIO215_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */
GPIO216_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */
DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
/* MSP2 for HDMI, pull down TXD, TCK, TFS */
DB8500_MUX_HOG("msp2_a_1", "msp2"),
DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
/*
* LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
* pull-up
* TODO: is this really correct? Snowball doesn't have a LCD.
*/
DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
DB8500_PIN_HOG("GPIO68_E1", in_pu),
DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
/*
* STMPE1601/tc35893 keypad IRQ GPIO 218
* TODO: set for snowball and HREF really??
*/
DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
/*
* UART0, we do not mux in u0 here.
* uart-0 pins gpio configuration should be kept intact to prevent
* a glitch in tx line when the tty dev is opened. Later these pins
* are configured to uart mop500_pins_uart0
*/
DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
/*
* Mux in UART2 on altfunction C and set pull-ups.
* TODO: is this used on U8500 variants and Snowball really?
* The setting on GPIO31 conflicts with magnetometer use on hrefv60
*/
DB8500_MUX_HOG("u2rxtx_c_1", "u2"),
DB8500_MUX_HOG("u2ctsrts_c_1", "u2"),
DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */
DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */
DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */
DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */
/*
* The following pin sets were known as "runtime pins" before being
* converted to the pinctrl model. Here we model them as "default"
* states.
*/
/* Mux in UART0 after initialization */
DB8500_MUX("u0_a_1", "u0", "uart0"),
DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
/* UART0 sleep state */
DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
/* MSP1 for ALSA codec */
DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
/* MSP1 sleep state */
DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
/* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
/* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
/* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
/* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
/* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
/* Mux in SDI2 (here called MC2) used for for PoP eMMC */
DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
/* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
/* Mux in USB pins, drive STP high */
DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
/* Mux in SPI2 pins on the "other C1" altfunction */
DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
};
/*
* I2C
* These are specifically for the MOP500 and HREFP (pre-v60) version of the
* board, which utilized a TC35892 GPIO expander instead of using a lot of
* on-chip pins as the HREFv60 and later does.
*/
static UX500_PINS(mop500_pins_i2c0,
GPIO147_I2C0_SCL |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
GPIO148_I2C0_SDA |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
);
static UX500_PINS(mop500_pins_i2c1,
GPIO16_I2C1_SCL |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
GPIO17_I2C1_SDA |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
);
static UX500_PINS(mop500_pins_i2c2,
GPIO10_I2C2_SDA |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
GPIO11_I2C2_SCL |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
);
static UX500_PINS(mop500_pins_i2c3,
GPIO229_I2C3_SDA |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
GPIO230_I2C3_SCL |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
);
static UX500_PINS(mop500_pins_mcde_tvout,
GPIO78_LCD_D8,
GPIO79_LCD_D9,
GPIO80_LCD_D10,
GPIO81_LCD_D11,
GPIO150_LCDA_CLK,
);
static UX500_PINS(mop500_pins_mcde_hdmi,
GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP,
);
static UX500_PINS(mop500_pins_ske,
GPIO153_KP_I7 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
GPIO154_KP_I6 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
GPIO155_KP_I5 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
GPIO156_KP_I4 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
GPIO161_KP_I3 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
GPIO162_KP_I2 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
GPIO163_KP_I1 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
GPIO164_KP_I0 | PIN_INPUT_PULLDOWN | PIN_SLPM_INPUT_PULLUP,
GPIO157_KP_O7 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
GPIO158_KP_O6 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
GPIO159_KP_O5 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
GPIO160_KP_O4 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
GPIO165_KP_O3 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
GPIO166_KP_O2 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
GPIO167_KP_O1 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
GPIO168_KP_O0 | PIN_INPUT_PULLUP | PIN_SLPM_OUTPUT_LOW,
);
/* sdi0 (removable MMC/SD/SDIO cards) */
static UX500_PINS(mop500_pins_sdi0,
GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
);
/* sdi1 (WLAN CW1200) */
static UX500_PINS(mop500_pins_sdi1,
GPIO208_MC1_CLK | PIN_OUTPUT_LOW,
GPIO209_MC1_FBCLK | PIN_INPUT_NOPULL,
GPIO210_MC1_CMD | PIN_INPUT_PULLUP,
GPIO211_MC1_DAT0 | PIN_INPUT_PULLUP,
GPIO212_MC1_DAT1 | PIN_INPUT_PULLUP,
GPIO213_MC1_DAT2 | PIN_INPUT_PULLUP,
GPIO214_MC1_DAT3 | PIN_INPUT_PULLUP,
);
/* sdi2 (POP eMMC) */
static UX500_PINS(mop500_pins_sdi2,
GPIO128_MC2_CLK | PIN_OUTPUT_LOW,
GPIO129_MC2_CMD | PIN_INPUT_PULLUP,
GPIO130_MC2_FBCLK | PIN_INPUT_NOPULL,
GPIO131_MC2_DAT0 | PIN_INPUT_PULLUP,
GPIO132_MC2_DAT1 | PIN_INPUT_PULLUP,
GPIO133_MC2_DAT2 | PIN_INPUT_PULLUP,
GPIO134_MC2_DAT3 | PIN_INPUT_PULLUP,
GPIO135_MC2_DAT4 | PIN_INPUT_PULLUP,
GPIO136_MC2_DAT5 | PIN_INPUT_PULLUP,
GPIO137_MC2_DAT6 | PIN_INPUT_PULLUP,
GPIO138_MC2_DAT7 | PIN_INPUT_PULLUP,
);
/* sdi4 (PCB eMMC) */
static UX500_PINS(mop500_pins_sdi4,
GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
);
/* USB */
static UX500_PINS(mop500_pins_usb,
GPIO256_USB_NXT,
GPIO257_USB_STP | PIN_OUTPUT_HIGH,
GPIO258_USB_XCLK,
GPIO259_USB_DIR,
GPIO260_USB_DAT7,
GPIO261_USB_DAT6,
GPIO262_USB_DAT5,
GPIO263_USB_DAT4,
GPIO264_USB_DAT3,
GPIO265_USB_DAT2,
GPIO266_USB_DAT1,
GPIO267_USB_DAT0,
);
/* SPI2 */
static UX500_PINS(mop500_pins_spi2,
GPIO216_GPIO | PIN_OUTPUT_HIGH,
GPIO218_SPI2_RXD | PIN_INPUT_PULLDOWN,
GPIO215_SPI2_TXD | PIN_OUTPUT_LOW,
GPIO217_SPI2_CLK | PIN_OUTPUT_LOW,
);
static UX500_PINS(mop500_pins_sensors1p_v60,
GPIO217_GPIO| PIN_INPUT_PULLUP |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
GPIO145_GPIO | PIN_INPUT_PULLDOWN |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
GPIO139_GPIO | PIN_INPUT_PULLUP |
PIN_SLPM_GPIO | PIN_SLPM_INPUT_NOPULL,
);
static UX500_PINS(mop500_pins_sensors1p,
PIN_CFG_INPUT(GPIO_PROX_SENSOR, GPIO, NOPULL),
PIN_CFG_INPUT(GPIO_HAL_SENSOR, GPIO, NOPULL),
);
static struct ux500_pin_lookup mop500_runtime_pins[] = {
PIN_LOOKUP("mcde-tvout", &mop500_pins_mcde_tvout),
PIN_LOOKUP("av8100-hdmi", &mop500_pins_mcde_hdmi),
PIN_LOOKUP("nmk-i2c.0", &mop500_pins_i2c0),
PIN_LOOKUP("nmk-i2c.1", &mop500_pins_i2c1),
PIN_LOOKUP("nmk-i2c.2", &mop500_pins_i2c2),
PIN_LOOKUP("nmk-i2c.3", &mop500_pins_i2c3),
PIN_LOOKUP("sdi0", &mop500_pins_sdi0),
PIN_LOOKUP("sdi1", &mop500_pins_sdi1),
PIN_LOOKUP("sdi2", &mop500_pins_sdi2),
PIN_LOOKUP("sdi4", &mop500_pins_sdi4),
PIN_LOOKUP("musb-ux500.0", &mop500_pins_usb),
PIN_LOOKUP("spi2", &mop500_pins_spi2),
static struct pinctrl_map __initdata mop500_pinmap[] = {
/* Mux in SSP0, pull down RXD pin */
DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
DB8500_PIN_HOG("GPIO145_C13", pd),
/*
* XENON Flashgun on image processor GPIO (controlled from image
* processor firmware), mux in these image processor GPIO lines 0
* (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
* the pins.
*/
DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
DB8500_PIN_HOG("GPIO6_AF6", in_pu),
DB8500_PIN_HOG("GPIO7_AG5", in_pu),
/* TC35892 IRQ, pull up the line, let the driver mux in the pin */
DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
/* Mux in UART1 and set the pull-ups */
DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
DB8500_MUX_HOG("u1ctsrts_a_1", "u1"),
DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */
DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */
/*
* Runtime stuff: make it possible to mux in the SKE keypad
* and bias the pins
*/
DB8500_MUX("kp_a_2", "kp", "ske"),
DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
/* Mux in and drive the SDI0 DAT31DIR line high at runtime */
DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
};
static struct ux500_pin_lookup mop500_runtime_pins_v60[] = {
PIN_LOOKUP("ske", &mop500_pins_ske),
PIN_LOOKUP("gpio-keys.0", &mop500_pins_sensors1p_v60),
/*
* The HREFv60 series of platforms is using available pins on the DB8500
* insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
* and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
*/
static struct pinctrl_map __initdata hrefv60_pinmap[] = {
/* Drive WLAN_ENA low */
DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
/*
* XENON Flashgun on image processor GPIO (controlled from image
* processor firmware), mux in these image processor GPIO lines 0
* (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
* LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
* from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
*/
DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
/* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
/*
* Display Interface 1 uses GPIO 65 for RST (reset).
* Display Interface 2 uses GPIO 66 for RST (reset).
* Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
*/
DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
/*
* Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
* GPIO 67 for interrupts. Pull-up the IRQ line and drive both
* reset signals low.
*/
DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
/*
* Drive D19-D23 for the ETM PTM trace interface low,
* (presumably pins are unconnected therefore grounded here,
* the "other alt C1" setting enables these pins)
*/
DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
/* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
/* NFC ENA and RESET to low, pulldown IRQ line */
DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
/*
* SKE keyboard partly on alt A and partly on "Other alt C1"
* Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
* rows of 6 keys, then pull up force sensing interrup and
* drive reset and force sensing WU low.
*/
DB8500_MUX_HOG("kp_a_1", "kp"),
DB8500_MUX_HOG("kp_oc1_1", "kp"),
DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
/* DiPro Sensor interrupt */
DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
/* Audio Amplifier HF enable */
DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
/* GBF interface, pull low to reset state */
DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
/* MSP : HDTV INTERFACE GPIO line */
DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
/* Accelerometer interrupt lines */
DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
/* SD card detect GPIO pin */
DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
/*
* Runtime stuff
* Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
* etc.
*/
DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
/*
* Make it possible to mux in the SKE keypad and bias the pins
* FIXME: what's the point with this on HREFv60? KP/SKE is already
* muxed in at another place! Enabling this will bork.
*/
DB8500_MUX("kp_a_2", "kp", "ske"),
DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
};
static struct ux500_pin_lookup mop500_runtime_pins_pre_v60[] = {
PIN_LOOKUP("ske", &mop500_pins_ske),
PIN_LOOKUP("gpio-keys.0", &mop500_pins_sensors1p),
static struct pinctrl_map __initdata u9500_pinmap[] = {
/* Mux in UART1 (just RX/TX) and set the pull-ups */
DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
DB8500_PIN_HOG("GPIO4_AH6", in_pu),
DB8500_PIN_HOG("GPIO5_AG6", out_hi),
/* WLAN_IRQ line */
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
/* HSI */
DB8500_MUX_HOG("hsir_a_1", "hsi"),
DB8500_MUX_HOG("hsit_a_1", "hsi"),
DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
};
static struct pinctrl_map __initdata u8500_pinmap[] = {
DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
};
static struct pinctrl_map __initdata snowball_pinmap[] = {
/* Mux in SSP0 connected to AB8500, pull down RXD pin */
DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
DB8500_PIN_HOG("GPIO145_C13", pd),
/* Always drive the MC0 DAT31DIR line high on these boards */
DB8500_PIN_HOG("GPIO21_AB3", out_hi),
/* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
DB8500_MUX_HOG("sm_b_1", "sm"),
/* Drive RSTn_LAN high */
DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
/* Accelerometer/Magnetometer */
DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
/* WLAN/GBF */
DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
};
/*
@ -444,64 +470,45 @@ int pins_for_u9500(void)
return 0;
}
void __init mop500_pins_init(void)
static void __init mop500_href_family_pinmaps_init(void)
{
nmk_config_pins(mop500_pins_common,
ARRAY_SIZE(mop500_pins_common));
ux500_pins_add(mop500_runtime_pins, ARRAY_SIZE(mop500_runtime_pins));
ux500_pins_add(mop500_runtime_pins_pre_v60,
ARRAY_SIZE(mop500_runtime_pins_pre_v60));
switch (pinsfor) {
case PINS_FOR_U9500:
nmk_config_pins(u9500_pins, ARRAY_SIZE(u9500_pins));
pinctrl_register_mappings(u9500_pinmap,
ARRAY_SIZE(u9500_pinmap));
break;
case PINS_FOR_DEFAULT:
nmk_config_pins(u8500_pins, ARRAY_SIZE(u8500_pins));
default:
break;
}
nmk_config_pins(mop500_pins_default,
ARRAY_SIZE(mop500_pins_default));
}
void __init snowball_pins_init(void)
{
nmk_config_pins(mop500_pins_common,
ARRAY_SIZE(mop500_pins_common));
ux500_pins_add(mop500_runtime_pins, ARRAY_SIZE(mop500_runtime_pins));
nmk_config_pins(u8500_pins, ARRAY_SIZE(u8500_pins));
nmk_config_pins(snowball_pins, ARRAY_SIZE(snowball_pins));
}
void __init hrefv60_pins_init(void)
{
nmk_config_pins(mop500_pins_common,
ARRAY_SIZE(mop500_pins_common));
ux500_pins_add(mop500_runtime_pins, ARRAY_SIZE(mop500_runtime_pins));
ux500_pins_add(mop500_runtime_pins_v60,
ARRAY_SIZE(mop500_runtime_pins_v60));
nmk_config_pins(hrefv60_pins,
ARRAY_SIZE(hrefv60_pins));
switch (pinsfor) {
case PINS_FOR_U9500:
nmk_config_pins(u9500_pins, ARRAY_SIZE(u9500_pins));
break;
case PINS_FOR_DEFAULT:
nmk_config_pins(u8500_pins, ARRAY_SIZE(u8500_pins));
pinctrl_register_mappings(u8500_pinmap,
ARRAY_SIZE(u8500_pinmap));
default:
break;
}
}
void __init mop500_pinmaps_init(void)
{
pinctrl_register_mappings(mop500_family_pinmap,
ARRAY_SIZE(mop500_family_pinmap));
pinctrl_register_mappings(mop500_pinmap,
ARRAY_SIZE(mop500_pinmap));
mop500_href_family_pinmaps_init();
}
void __init snowball_pinmaps_init(void)
{
pinctrl_register_mappings(mop500_family_pinmap,
ARRAY_SIZE(mop500_family_pinmap));
pinctrl_register_mappings(snowball_pinmap,
ARRAY_SIZE(snowball_pinmap));
pinctrl_register_mappings(u8500_pinmap,
ARRAY_SIZE(u8500_pinmap));
}
void __init hrefv60_pinmaps_init(void)
{
pinctrl_register_mappings(mop500_family_pinmap,
ARRAY_SIZE(mop500_family_pinmap));
pinctrl_register_mappings(hrefv60_pinmap,
ARRAY_SIZE(hrefv60_pinmap));
mop500_href_family_pinmaps_init();
}

83
arch/arm/mach-ux500/board-mop500.c
View file

@ -1,3 +1,4 @@
/*
* Copyright (C) 2008-2009 ST-Ericsson
*
@ -29,18 +30,17 @@
#include <linux/smsc911x.h>
#include <linux/gpio_keys.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/leds.h>
#include <linux/pinctrl/consumer.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <plat/i2c.h>
#include <plat/ste_dma40.h>
#include <plat/pincfg.h>
#include <plat/gpio-nomadik.h>
#include <mach/hardware.h>
@ -48,7 +48,6 @@
#include <mach/devices.h>
#include <mach/irqs.h>
#include "pins-db8500.h"
#include "ste-dma40-db8500.h"
#include "devices-db8500.h"
#include "board-mop500.h"
@ -521,14 +520,6 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
};
#endif
static pin_cfg_t mop500_pins_uart0[] = {
GPIO0_U0_CTSn | PIN_INPUT_PULLUP,
GPIO1_U0_RTSn | PIN_OUTPUT_HIGH,
GPIO2_U0_RXD | PIN_INPUT_PULLUP,
GPIO3_U0_TXD | PIN_OUTPUT_HIGH,
};
#define PRCC_K_SOFTRST_SET 0x18
#define PRCC_K_SOFTRST_CLEAR 0x1C
static void ux500_uart0_reset(void)
@ -549,24 +540,33 @@ static void ux500_uart0_reset(void)
udelay(1);
}
/* This needs to be referenced by callbacks */
struct pinctrl *u0_p;
struct pinctrl_state *u0_def;
struct pinctrl_state *u0_sleep;
static void ux500_uart0_init(void)
{
int ret;
ret = nmk_config_pins(mop500_pins_uart0,
ARRAY_SIZE(mop500_pins_uart0));
if (ret < 0)
pr_err("pl011: uart pins_enable failed\n");
if (IS_ERR(u0_p) || IS_ERR(u0_def))
return;
ret = pinctrl_select_state(u0_p, u0_def);
if (ret)
pr_err("could not set UART0 defstate\n");
}
static void ux500_uart0_exit(void)
{
int ret;
ret = nmk_config_pins_sleep(mop500_pins_uart0,
ARRAY_SIZE(mop500_pins_uart0));
if (ret < 0)
pr_err("pl011: uart pins_disable failed\n");
if (IS_ERR(u0_p) || IS_ERR(u0_sleep))
return;
ret = pinctrl_select_state(u0_p, u0_sleep);
if (ret)
pr_err("could not set UART0 idlestate\n");
}
static struct amba_pl011_data uart0_plat = {
@ -598,7 +598,28 @@ static struct amba_pl011_data uart2_plat = {
static void __init mop500_uart_init(struct device *parent)
{
db8500_add_uart0(parent, &uart0_plat);
struct amba_device *uart0_device;
uart0_device = db8500_add_uart0(parent, &uart0_plat);
if (uart0_device) {
u0_p = pinctrl_get(&uart0_device->dev);
if (IS_ERR(u0_p))
dev_err(&uart0_device->dev,
"could not get UART0 pinctrl\n");
else {
u0_def = pinctrl_lookup_state(u0_p,
PINCTRL_STATE_DEFAULT);
if (IS_ERR(u0_def)) {
dev_err(&uart0_device->dev,
"could not get UART0 defstate\n");
}
u0_sleep = pinctrl_lookup_state(u0_p,
PINCTRL_STATE_SLEEP);
if (IS_ERR(u0_sleep))
dev_err(&uart0_device->dev,
"could not get UART0 idlestate\n");
}
}
db8500_add_uart1(parent, &uart1_plat);
db8500_add_uart2(parent, &uart2_plat);
}
@ -618,10 +639,9 @@ static void __init mop500_init_machine(void)
mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
mop500_pinmaps_init();
parent = u8500_init_devices();
mop500_pins_init();
/* FIXME: parent of ab8500 should be prcmu */
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
mop500_platform_devs[i]->dev.parent = parent;
@ -651,10 +671,9 @@ static void __init snowball_init_machine(void)
int i2c0_devs;
int i;
snowball_pinmaps_init();
parent = u8500_init_devices();
snowball_pins_init();
for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
snowball_platform_devs[i]->dev.parent = parent;
@ -689,10 +708,9 @@ static void __init hrefv60_init_machine(void)
*/
mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
hrefv60_pinmaps_init();
parent = u8500_init_devices();
hrefv60_pins_init();
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
mop500_platform_devs[i]->dev.parent = parent;
@ -781,6 +799,14 @@ static void __init u8500_init_machine(void)
int i2c0_devs;
int i;
/* Pinmaps must be in place before devices register */
if (of_machine_is_compatible("st-ericsson,mop500"))
mop500_pinmaps_init();
else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
snowball_pinmaps_init();
else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
hrefv60_pinmaps_init();
parent = u8500_init_devices();
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@ -794,14 +820,12 @@ static void __init u8500_init_machine(void)
if (of_machine_is_compatible("st-ericsson,mop500")) {
mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
mop500_pins_init();
platform_add_devices(mop500_platform_devs,
ARRAY_SIZE(mop500_platform_devs));
mop500_sdi_init(parent);
} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
snowball_pins_init();
platform_add_devices(snowball_platform_devs,
ARRAY_SIZE(snowball_platform_devs));
@ -814,7 +838,6 @@ static void __init u8500_init_machine(void)
*/
mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
hrefv60_pins_init();
platform_add_devices(mop500_platform_devs,
ARRAY_SIZE(mop500_platform_devs));

6
arch/arm/mach-ux500/board-mop500.h
View file

@ -85,9 +85,9 @@ extern void hrefv60_sdi_init(struct device *parent);
extern void mop500_sdi_tc35892_init(struct device *parent);
void __init mop500_u8500uib_init(void);
void __init mop500_stuib_init(void);
void __init mop500_pins_init(void);
void __init hrefv60_pins_init(void);
void __init snowball_pins_init(void);
void __init mop500_pinmaps_init(void);
void __init snowball_pinmaps_init(void);
void __init hrefv60_pinmaps_init(void);
void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
unsigned n);

1
arch/arm/mach-ux500/cpu-db8500.c
View file

@ -141,6 +141,7 @@ static void __init db8500_add_gpios(struct device *parent)
dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
IRQ_DB8500_GPIO0, &pdata);
dbx500_add_pinctrl(parent, "pinctrl-db8500");
}
static int usb_db8500_rx_dma_cfg[] = {

12
arch/arm/mach-ux500/devices-common.h
View file

@ -93,4 +93,16 @@ struct nmk_gpio_platform_data;
void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
int irq, struct nmk_gpio_platform_data *pdata);
static inline void
dbx500_add_pinctrl(struct device *parent, const char *name)
{
struct platform_device_info pdevinfo = {
.parent = parent,
.name = name,
.id = -1,
};
platform_device_register_full(&pdevinfo);
}
#endif

88
arch/arm/mach-ux500/pins.c
View file

@ -1,88 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL), version 2
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <plat/pincfg.h>
#include "pins.h"
static LIST_HEAD(pin_lookups);
static DEFINE_MUTEX(pin_lookups_mutex);
static DEFINE_SPINLOCK(pins_lock);
void __init ux500_pins_add(struct ux500_pin_lookup *pl, size_t num)
{
mutex_lock(&pin_lookups_mutex);
while (num--) {
list_add_tail(&pl->node, &pin_lookups);
pl++;
}
mutex_unlock(&pin_lookups_mutex);
}
struct ux500_pins *ux500_pins_get(const char *name)
{
struct ux500_pins *pins = NULL;
struct ux500_pin_lookup *pl;
mutex_lock(&pin_lookups_mutex);
list_for_each_entry(pl, &pin_lookups, node) {
if (!strcmp(pl->name, name)) {
pins = pl->pins;
goto out;
}
}
out:
mutex_unlock(&pin_lookups_mutex);
return pins;
}
int ux500_pins_enable(struct ux500_pins *pins)
{
unsigned long flags;
int ret = 0;
spin_lock_irqsave(&pins_lock, flags);
if (pins->usage++ == 0)
ret = nmk_config_pins(pins->cfg, pins->num);
spin_unlock_irqrestore(&pins_lock, flags);
return ret;
}
int ux500_pins_disable(struct ux500_pins *pins)
{
unsigned long flags;
int ret = 0;
spin_lock_irqsave(&pins_lock, flags);
if (WARN_ON(pins->usage == 0))
goto out;
if (--pins->usage == 0)
ret = nmk_config_pins_sleep(pins->cfg, pins->num);
out:
spin_unlock_irqrestore(&pins_lock, flags);
return ret;
}
void ux500_pins_put(struct ux500_pins *pins)
{
WARN_ON(!pins);
}

46
arch/arm/mach-ux500/pins.h
View file

@ -1,46 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL), version 2
*/
#ifndef __MACH_UX500_PINS_H
#define __MACH_UX500_PINS_H
#include <linux/list.h>
#include <plat/pincfg.h>
#define PIN_LOOKUP(_name, _pins) \
{ \
.name = _name, \
.pins = _pins, \
}
#define UX500_PINS(name, pins...) \
struct ux500_pins name = { \
.cfg = (pin_cfg_t[]) {pins}, \
.num = ARRAY_SIZE(((pin_cfg_t[]) {pins})), \
}
struct ux500_pins {
int usage;
int num;
pin_cfg_t *cfg;
};
struct ux500_pin_lookup {
struct list_head node;
const char *name;
struct ux500_pins *pins;
};
void __init ux500_pins_add(struct ux500_pin_lookup *pl, size_t num);
void __init ux500_offchip_gpio_init(struct ux500_pins *pins);
struct ux500_pins *ux500_pins_get(const char *name);
int ux500_pins_enable(struct ux500_pins *pins);
int ux500_pins_disable(struct ux500_pins *pins);
void ux500_pins_put(struct ux500_pins *pins);
int pins_for_u9500(void);
#endif

13
arch/arm/plat-nomadik/include/plat/pincfg.h
View file

@ -124,6 +124,19 @@ typedef unsigned long pin_cfg_t;
#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
#define PIN_GPIOMODE_SHIFT 26
#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
#define PIN_SLEEPMODE_SHIFT 27
#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)

1
drivers/gpio/Makefile
View file

@ -36,7 +36,6 @@ obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o
obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o

10
drivers/pinctrl/Kconfig
View file

@ -64,6 +64,16 @@ config PINCTRL_IMX28
select PINCONF
select PINCTRL_MXS
config PINCTRL_NOMADIK
bool "Nomadik pin controller driver"
depends on ARCH_U8500
select PINMUX
select PINCONF
config PINCTRL_DB8500
bool "DB8500 pin controller driver"
depends on PINCTRL_NOMADIK && ARCH_U8500
config PINCTRL_PXA168
bool "PXA168 pin controller driver"
depends on ARCH_MMP

2
drivers/pinctrl/Makefile
View file

@ -16,6 +16,8 @@ obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o

857
drivers/pinctrl/pinctrl-nomadik-db8500.c Normal file
View file

@ -0,0 +1,857 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-nomadik.h"
/* All the pins that can be used for GPIO and some other functions */
#define _GPIO(offset) (offset)
#define DB8500_PIN_AJ5 _GPIO(0)
#define DB8500_PIN_AJ3 _GPIO(1)
#define DB8500_PIN_AH4 _GPIO(2)
#define DB8500_PIN_AH3 _GPIO(3)
#define DB8500_PIN_AH6 _GPIO(4)
#define DB8500_PIN_AG6 _GPIO(5)
#define DB8500_PIN_AF6 _GPIO(6)
#define DB8500_PIN_AG5 _GPIO(7)
#define DB8500_PIN_AD5 _GPIO(8)
#define DB8500_PIN_AE4 _GPIO(9)
#define DB8500_PIN_AF5 _GPIO(10)
#define DB8500_PIN_AG4 _GPIO(11)
#define DB8500_PIN_AC4 _GPIO(12)
#define DB8500_PIN_AF3 _GPIO(13)
#define DB8500_PIN_AE3 _GPIO(14)
#define DB8500_PIN_AC3 _GPIO(15)
#define DB8500_PIN_AD3 _GPIO(16)
#define DB8500_PIN_AD4 _GPIO(17)
#define DB8500_PIN_AC2 _GPIO(18)
#define DB8500_PIN_AC1 _GPIO(19)
#define DB8500_PIN_AB4 _GPIO(20)
#define DB8500_PIN_AB3 _GPIO(21)
#define DB8500_PIN_AA3 _GPIO(22)
#define DB8500_PIN_AA4 _GPIO(23)
#define DB8500_PIN_AB2 _GPIO(24)
#define DB8500_PIN_Y4 _GPIO(25)
#define DB8500_PIN_Y2 _GPIO(26)
#define DB8500_PIN_AA2 _GPIO(27)
#define DB8500_PIN_AA1 _GPIO(28)
#define DB8500_PIN_W2 _GPIO(29)
#define DB8500_PIN_W3 _GPIO(30)
#define DB8500_PIN_V3 _GPIO(31)
#define DB8500_PIN_V2 _GPIO(32)
#define DB8500_PIN_AF2 _GPIO(33)
#define DB8500_PIN_AE1 _GPIO(34)
#define DB8500_PIN_AE2 _GPIO(35)
#define DB8500_PIN_AG2 _GPIO(36)
/* Hole */
#define DB8500_PIN_F3 _GPIO(64)
#define DB8500_PIN_F1 _GPIO(65)
#define DB8500_PIN_G3 _GPIO(66)
#define DB8500_PIN_G2 _GPIO(67)
#define DB8500_PIN_E1 _GPIO(68)
#define DB8500_PIN_E2 _GPIO(69)
#define DB8500_PIN_G5 _GPIO(70)
#define DB8500_PIN_G4 _GPIO(71)
#define DB8500_PIN_H4 _GPIO(72)
#define DB8500_PIN_H3 _GPIO(73)
#define DB8500_PIN_J3 _GPIO(74)
#define DB8500_PIN_H2 _GPIO(75)
#define DB8500_PIN_J2 _GPIO(76)
#define DB8500_PIN_H1 _GPIO(77)
#define DB8500_PIN_F4 _GPIO(78)
#define DB8500_PIN_E3 _GPIO(79)
#define DB8500_PIN_E4 _GPIO(80)
#define DB8500_PIN_D2 _GPIO(81)
#define DB8500_PIN_C1 _GPIO(82)
#define DB8500_PIN_D3 _GPIO(83)
#define DB8500_PIN_C2 _GPIO(84)
#define DB8500_PIN_D5 _GPIO(85)
#define DB8500_PIN_C6 _GPIO(86)
#define DB8500_PIN_B3 _GPIO(87)
#define DB8500_PIN_C4 _GPIO(88)
#define DB8500_PIN_E6 _GPIO(89)
#define DB8500_PIN_A3 _GPIO(90)
#define DB8500_PIN_B6 _GPIO(91)
#define DB8500_PIN_D6 _GPIO(92)
#define DB8500_PIN_B7 _GPIO(93)
#define DB8500_PIN_D7 _GPIO(94)
#define DB8500_PIN_E8 _GPIO(95)
#define DB8500_PIN_D8 _GPIO(96)
#define DB8500_PIN_D9 _GPIO(97)
/* Hole */
#define DB8500_PIN_A5 _GPIO(128)
#define DB8500_PIN_B4 _GPIO(129)
#define DB8500_PIN_C8 _GPIO(130)
#define DB8500_PIN_A12 _GPIO(131)
#define DB8500_PIN_C10 _GPIO(132)
#define DB8500_PIN_B10 _GPIO(133)
#define DB8500_PIN_B9 _GPIO(134)
#define DB8500_PIN_A9 _GPIO(135)
#define DB8500_PIN_C7 _GPIO(136)
#define DB8500_PIN_A7 _GPIO(137)
#define DB8500_PIN_C5 _GPIO(138)
#define DB8500_PIN_C9 _GPIO(139)
#define DB8500_PIN_B11 _GPIO(140)
#define DB8500_PIN_C12 _GPIO(141)
#define DB8500_PIN_C11 _GPIO(142)
#define DB8500_PIN_D12 _GPIO(143)
#define DB8500_PIN_B13 _GPIO(144)
#define DB8500_PIN_C13 _GPIO(145)
#define DB8500_PIN_D13 _GPIO(146)
#define DB8500_PIN_C15 _GPIO(147)
#define DB8500_PIN_B16 _GPIO(148)
#define DB8500_PIN_B14 _GPIO(149)
#define DB8500_PIN_C14 _GPIO(150)
#define DB8500_PIN_D17 _GPIO(151)
#define DB8500_PIN_D16 _GPIO(152)
#define DB8500_PIN_B17 _GPIO(153)
#define DB8500_PIN_C16 _GPIO(154)
#define DB8500_PIN_C19 _GPIO(155)
#define DB8500_PIN_C17 _GPIO(156)
#define DB8500_PIN_A18 _GPIO(157)
#define DB8500_PIN_C18 _GPIO(158)
#define DB8500_PIN_B19 _GPIO(159)
#define DB8500_PIN_B20 _GPIO(160)
#define DB8500_PIN_D21 _GPIO(161)
#define DB8500_PIN_D20 _GPIO(162)
#define DB8500_PIN_C20 _GPIO(163)
#define DB8500_PIN_B21 _GPIO(164)
#define DB8500_PIN_C21 _GPIO(165)
#define DB8500_PIN_A22 _GPIO(166)
#define DB8500_PIN_B24 _GPIO(167)
#define DB8500_PIN_C22 _GPIO(168)
#define DB8500_PIN_D22 _GPIO(169)
#define DB8500_PIN_C23 _GPIO(170)
#define DB8500_PIN_D23 _GPIO(171)
/* Hole */
#define DB8500_PIN_AJ27 _GPIO(192)
#define DB8500_PIN_AH27 _GPIO(193)
#define DB8500_PIN_AF27 _GPIO(194)
#define DB8500_PIN_AG28 _GPIO(195)
#define DB8500_PIN_AG26 _GPIO(196)
#define DB8500_PIN_AH24 _GPIO(197)
#define DB8500_PIN_AG25 _GPIO(198)
#define DB8500_PIN_AH23 _GPIO(199)
#define DB8500_PIN_AH26 _GPIO(200)
#define DB8500_PIN_AF24 _GPIO(201)
#define DB8500_PIN_AF25 _GPIO(202)
#define DB8500_PIN_AE23 _GPIO(203)
#define DB8500_PIN_AF23 _GPIO(204)
#define DB8500_PIN_AG23 _GPIO(205)
#define DB8500_PIN_AG24 _GPIO(206)
#define DB8500_PIN_AJ23 _GPIO(207)
#define DB8500_PIN_AH16 _GPIO(208)
#define DB8500_PIN_AG15 _GPIO(209)
#define DB8500_PIN_AJ15 _GPIO(210)
#define DB8500_PIN_AG14 _GPIO(211)
#define DB8500_PIN_AF13 _GPIO(212)
#define DB8500_PIN_AG13 _GPIO(213)
#define DB8500_PIN_AH15 _GPIO(214)
#define DB8500_PIN_AH13 _GPIO(215)
#define DB8500_PIN_AG12 _GPIO(216)
#define DB8500_PIN_AH12 _GPIO(217)
#define DB8500_PIN_AH11 _GPIO(218)
#define DB8500_PIN_AG10 _GPIO(219)
#define DB8500_PIN_AH10 _GPIO(220)
#define DB8500_PIN_AJ11 _GPIO(221)
#define DB8500_PIN_AJ9 _GPIO(222)
#define DB8500_PIN_AH9 _GPIO(223)
#define DB8500_PIN_AG9 _GPIO(224)
#define DB8500_PIN_AG8 _GPIO(225)
#define DB8500_PIN_AF8 _GPIO(226)
#define DB8500_PIN_AH7 _GPIO(227)
#define DB8500_PIN_AJ6 _GPIO(228)
#define DB8500_PIN_AG7 _GPIO(229)
#define DB8500_PIN_AF7 _GPIO(230)
/* Hole */
#define DB8500_PIN_AF28 _GPIO(256)
#define DB8500_PIN_AE29 _GPIO(257)
#define DB8500_PIN_AD29 _GPIO(258)
#define DB8500_PIN_AC29 _GPIO(259)
#define DB8500_PIN_AD28 _GPIO(260)
#define DB8500_PIN_AD26 _GPIO(261)
#define DB8500_PIN_AE26 _GPIO(262)
#define DB8500_PIN_AG29 _GPIO(263)
#define DB8500_PIN_AE27 _GPIO(264)
#define DB8500_PIN_AD27 _GPIO(265)
#define DB8500_PIN_AC28 _GPIO(266)
#define DB8500_PIN_AC27 _GPIO(267)
/*
* The names of the pins are denoted by GPIO number and ball name, even
* though they can be used for other things than GPIO, this is the first
* column in the table of the data sheet and often used on schematics and
* such.
*/
static const struct pinctrl_pin_desc nmk_db8500_pins[] = {
PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"),
PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"),
PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"),
PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"),
PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"),
PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"),
PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"),
PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"),
PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"),
PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"),
PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"),
PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"),
PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"),
PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"),
PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"),
PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"),
PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"),
PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"),
PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"),
PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"),
PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"),
PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"),
PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"),
PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"),
PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"),
PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"),
PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"),
PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"),
PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"),
PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"),
PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"),
PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"),
PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"),
PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"),
PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"),
PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"),
PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"),
/* Hole */
PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"),
PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"),
PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"),
PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"),
PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"),
PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"),
PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"),
PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"),
PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"),
PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"),
PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"),
PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"),
PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"),
PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"),
PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"),
PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"),
PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"),
PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"),
PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"),
PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"),
PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"),
PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"),
PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"),
PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"),
PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"),
PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"),
PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"),
PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"),
PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"),
PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"),
PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"),
PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"),
PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"),
PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"),
/* Hole */
PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"),
PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"),
PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"),
PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"),
PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"),
PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"),
PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"),
PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"),
PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"),
PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"),
PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"),
PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"),
PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"),
PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"),
PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"),
PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"),
PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"),
PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"),
PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"),
PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"),
PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"),
PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"),
PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"),
PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"),
PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"),
PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"),
PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"),
PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"),
PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"),
PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"),
PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"),
PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"),
PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"),
PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"),
PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"),
PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"),
PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"),
PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"),
PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"),
PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"),
PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"),
PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"),
PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"),
PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"),
/* Hole */
PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"),
PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"),
PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"),
PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"),
PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"),
PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"),
PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"),
PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"),
PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"),
PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"),
PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"),
PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"),
PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"),
PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"),
PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"),
PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"),
PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"),
PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"),
PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"),
PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"),
PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"),
PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"),
PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"),
PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"),
PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"),
PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"),
PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"),
PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"),
PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"),
PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"),
PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"),
PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"),
PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"),
PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"),
PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"),
PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"),
PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"),
PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"),
PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"),
/* Hole */
PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"),
PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"),
PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"),
PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"),
PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"),
PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"),
PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"),
PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"),
PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"),
PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"),
PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"),
PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"),
};
#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \
.pin_base = b, .npins = c }
/*
* This matches the 32-pin gpio chips registered by the GPIO portion. This
* cannot be const since we assign the struct gpio_chip * pointer at runtime.
*/
static struct pinctrl_gpio_range nmk_db8500_ranges[] = {
DB8500_GPIO_RANGE(0, 0, 32),
DB8500_GPIO_RANGE(1, 32, 5),
DB8500_GPIO_RANGE(2, 64, 32),
DB8500_GPIO_RANGE(3, 96, 2),
DB8500_GPIO_RANGE(4, 128, 32),
DB8500_GPIO_RANGE(5, 160, 12),
DB8500_GPIO_RANGE(6, 192, 32),
DB8500_GPIO_RANGE(7, 224, 7),
DB8500_GPIO_RANGE(8, 256, 12),
};
/*
* Read the pin group names like this:
* u0_a_1 = first groups of pins for uart0 on alt function a
* i2c2_b_2 = second group of pins for i2c2 on alt function b
*
* The groups are arranged as sets per altfunction column, so we can
* mux in one group at a time by selecting the same altfunction for them
* all. When functions require pins on different altfunctions, you need
* to combine several groups.
*/
/* Altfunction A column */
static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
DB8500_PIN_AH4, DB8500_PIN_AH3 };
static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
/* Image processor I2C line, this is driven by image processor firmware */
static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 };
static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
/* Basic pins of the MMC/SD card 0 interface */
static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
/* Often only 4 bits are used, then these are not needed (only used for MMC) */
static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
DB8500_PIN_V3, DB8500_PIN_V2};
static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 };
/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 };
/* LCD interface */
static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
DB8500_PIN_G3, DB8500_PIN_G2 };
static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 };
static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 };
static const unsigned lcd_d0_d7_a_1_pins[] = {
DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 };
/* D8 thru D11 often used as TVOUT lines */
static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4,
DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 };
static const unsigned lcd_d12_d23_a_1_pins[] = {
DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5,
DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6,
DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 };
static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8,
DB8500_PIN_D8, DB8500_PIN_D9 };
static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 };
static const unsigned kp_a_2_pins[] = {
DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4,
DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10,
DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7,
DB8500_PIN_C5 };
static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
DB8500_PIN_C12, DB8500_PIN_C11 };
static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13,
DB8500_PIN_C13, DB8500_PIN_D13 };
static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 };
/*
* Image processor GPIO pins are named "ipgpio" and have their own
* numberspace
*/
static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 };
static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 };
/* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */
static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23,
DB8500_PIN_D23 };
/*
* This MSP cannot switch RX and TX, SCK in a separate group since this
* seems to be optional.
*/
static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 };
static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27,
DB8500_PIN_AG28, DB8500_PIN_AG26 };
static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25,
DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24,
DB8500_PIN_AJ23 };
/* MC1 has only 4 data pins, designed for SD or SDIO exclusively */
static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
DB8500_PIN_AH15 };
static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
DB8500_PIN_AH12, DB8500_PIN_AH11 };
static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10 };
static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ11, DB8500_PIN_AJ9,
DB8500_PIN_AH9, DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 };
static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 };
static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29,
DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26,
DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27,
DB8500_PIN_AC28, DB8500_PIN_AC27 };
/* Altfunction B column */
static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 };
static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
/* Just RX and TX for UART2 */
static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 };
static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 };
static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 };
static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 };
static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4,
DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 };
static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
DB8500_PIN_V3, DB8500_PIN_V2 };
static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2,
DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1,
DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2,
DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8,
DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9,
DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5,
DB8500_PIN_C9, DB8500_PIN_B14 };
/* This chip select pin can be "ps0" in alt B so have it separately */
static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 };
static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 };
static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 };
static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 };
static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 };
static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22,
DB8500_PIN_C23, DB8500_PIN_D23 };
static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 };
static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 };
static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13,
DB8500_PIN_AG13, DB8500_PIN_AH15 };
static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10,
DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9,
DB8500_PIN_AG8 };
static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 };
static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 };
static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 };
/* Altfunction C column */
static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 };
static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 };
static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 };
static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 };
static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 };
static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 };
static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
/* Optional 4-bit Memory Stick interface */
static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 };
static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 };
static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 };
static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1,
DB8500_PIN_AE2, DB8500_PIN_AG2 };
static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 };
static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 };
static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 };
static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 };
static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 };
static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 };
static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 };
static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 };
static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 };
static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 };
static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 };
static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
DB8500_PIN_D9 };
static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 };
static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16,
DB8500_PIN_C23, DB8500_PIN_D23 };
static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 };
static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 };
static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17,
DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 };
static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 };
static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 };
static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21,
DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 };
static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 };
static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 };
static const unsigned clkout_c_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12 };
static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 };
static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9,
DB8500_PIN_AG9, DB8500_PIN_AG8 };
static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 };
static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
/* Other C1 column */
static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
DB8500_PIN_D6, DB8500_PIN_B7 };
static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
DB8500_PIN_AH12, DB8500_PIN_AH11 };
#define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
static const struct nmk_pingroup nmk_db8500_groups[] = {
/* Altfunction A column */
DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
/* Altfunction B column */
DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
/* Altfunction C column */
DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(clkout_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C),
/* Other alt C1 column, these are still configured as alt C */
DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C),
};
/* We use this macro to define the groups applicable to a function */
#define DB8500_FUNC_GROUPS(a, b...) \
static const char * const a##_groups[] = { b };
DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1");
/*
* UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however
* only available on two pins in alternative function C
*/
DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1",
"u2rxtx_c_2", "u2rxtx_c_3");
DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
/*
* MSP0 can only be on a certain set of pins, but the TX/RX pins can be
* switched around by selecting the altfunction A or B. The SCK pin is
* only available on the altfunction B.
*/
DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1",
"msp0txrx_b_1", "msp0sck_b_1");
DB8500_FUNC_GROUPS(mc0, "mc0_a_1");
/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */
DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
"lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");
DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1");
/* The image processor has 8 GPIO pins that can be muxed out */
DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
"ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1",
"ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1",
"ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2",
"ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2");
/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1");
DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1");
DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
DB8500_FUNC_GROUPS(usb, "usb_a_1");
DB8500_FUNC_GROUPS(trig, "trig_b_1");
DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1");
DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
/*
* The modem UART can output its RX and TX pins in some different places,
* so select one of each.
*/
DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2",
"uartmodrx_c_1", "uartmod_tx_c_1");
DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1");
DB8500_FUNC_GROUPS(spi3, "spi3_b_1");
/* Select between CS0 on alt B or PS1 on alt C */
DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcleale_c_1", "smps1_c_1");
DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1");
DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
DB8500_FUNC_GROUPS(spi1, "spi1_b_1");
DB8500_FUNC_GROUPS(mc3, "mc3_b_1");
DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1");
DB8500_FUNC_GROUPS(slim0, "slim0_c_1");
DB8500_FUNC_GROUPS(ms, "ms_c_1");
DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1");
DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2");
DB8500_FUNC_GROUPS(mc5, "mc5_c_1");
DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2");
DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2");
DB8500_FUNC_GROUPS(spi0, "spi0_c_1");
DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1");
#define FUNCTION(fname) \
{ \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
static const struct nmk_function nmk_db8500_functions[] = {
FUNCTION(u0),
FUNCTION(u1),
FUNCTION(u2),
FUNCTION(ipi2c),
FUNCTION(msp0),
FUNCTION(mc0),
FUNCTION(msp1),
FUNCTION(lcdb),
FUNCTION(lcd),
FUNCTION(kp),
FUNCTION(mc2),
FUNCTION(ssp1),
FUNCTION(ssp0),
FUNCTION(i2c0),
FUNCTION(ipgpio),
FUNCTION(msp2),
FUNCTION(mc4),
FUNCTION(mc1),
FUNCTION(hsi),
FUNCTION(clkout),
FUNCTION(usb),
FUNCTION(trig),
FUNCTION(i2c4),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(uartmod),
FUNCTION(stmmod),
FUNCTION(spi3),
FUNCTION(sm),
FUNCTION(lcda),
FUNCTION(ddrtrig),
FUNCTION(pwl),
FUNCTION(spi1),
FUNCTION(mc3),
FUNCTION(ipjtag),
FUNCTION(slim0),
FUNCTION(ms),
FUNCTION(iptrigout),
FUNCTION(stmape),
FUNCTION(mc5),
FUNCTION(usbsim),
FUNCTION(i2c3),
FUNCTION(spi0),
FUNCTION(spi2),
};
static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
.gpio_ranges = nmk_db8500_ranges,
.gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges),
.pins = nmk_db8500_pins,
.npins = ARRAY_SIZE(nmk_db8500_pins),
.functions = nmk_db8500_functions,
.nfunctions = ARRAY_SIZE(nmk_db8500_functions),
.groups = nmk_db8500_groups,
.ngroups = ARRAY_SIZE(nmk_db8500_groups),
};
void __devinit
nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
{
*soc = &nmk_db8500_soc;
}

564
drivers/gpio/gpio-nomadik.c → drivers/pinctrl/pinctrl-nomadik.c
View file

@ -24,12 +24,19 @@
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
/* Since we request GPIOs from ourself */
#include <linux/pinctrl/consumer.h>
#include <asm/mach/irq.h>
#include <plat/pincfg.h>
#include <plat/gpio-nomadik.h>
#include "pinctrl-nomadik.h"
/*
* The GPIO module in the Nomadik family of Systems-on-Chip is an
* AMBA device, managing 32 pins and alternate functions. The logic block
@ -64,6 +71,12 @@ struct nmk_gpio_chip {
u32 lowemi;
};
struct nmk_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
const struct nmk_pinctrl_soc_data *soc;
};
static struct nmk_gpio_chip *
nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
@ -864,6 +877,25 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
}
/* I/O Functions */
static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
{
/*
* Map back to global GPIO space and request muxing, the direction
* parameter does not matter for this controller.
*/
int gpio = chip->base + offset;
return pinctrl_request_gpio(gpio);
}
static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
{
int gpio = chip->base + offset;
pinctrl_free_gpio(gpio);
}
static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
{
struct nmk_gpio_chip *nmk_chip =
@ -934,14 +966,16 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
#include <linux/seq_file.h>
static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
unsigned offset, unsigned gpio)
{
int mode;
unsigned i;
unsigned gpio = chip->base;
int is_out;
const char *label = gpiochip_is_requested(chip, offset);
struct nmk_gpio_chip *nmk_chip =
container_of(chip, struct nmk_gpio_chip, chip);
int mode;
bool is_out;
bool pull;
u32 bit = 1 << offset;
const char *modes[] = {
[NMK_GPIO_ALT_GPIO] = "gpio",
[NMK_GPIO_ALT_A] = "altA",
@ -950,61 +984,70 @@ static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
};
clk_enable(nmk_chip->clk);
is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
mode = nmk_gpio_get_mode(gpio);
for (i = 0; i < chip->ngpio; i++, gpio++) {
const char *label = gpiochip_is_requested(chip, i);
bool pull;
u32 bit = 1 << i;
seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
gpio, label ?: "(none)",
is_out ? "out" : "in ",
chip->get
? (chip->get(chip, offset) ? "hi" : "lo")
: "? ",
(mode < 0) ? "unknown" : modes[mode],
pull ? "pull" : "none");
is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
mode = nmk_gpio_get_mode(gpio);
seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
gpio, label ?: "(none)",
is_out ? "out" : "in ",
chip->get
? (chip->get(chip, i) ? "hi" : "lo")
: "? ",
(mode < 0) ? "unknown" : modes[mode],
pull ? "pull" : "none");
if (label && !is_out) {
int irq = gpio_to_irq(gpio);
struct irq_desc *desc = irq_to_desc(irq);
if (label && !is_out) {
int irq = gpio_to_irq(gpio);
struct irq_desc *desc = irq_to_desc(irq);
/* This races with request_irq(), set_irq_type(),
* and set_irq_wake() ... but those are "rare".
*/
if (irq >= 0 && desc->action) {
char *trigger;
u32 bitmask = nmk_gpio_get_bitmask(gpio);
/* This races with request_irq(), set_irq_type(),
* and set_irq_wake() ... but those are "rare".
*/
if (irq >= 0 && desc->action) {
char *trigger;
u32 bitmask = nmk_gpio_get_bitmask(gpio);
if (nmk_chip->edge_rising & bitmask)
trigger = "edge-rising";
else if (nmk_chip->edge_falling & bitmask)
trigger = "edge-falling";
else
trigger = "edge-undefined";
if (nmk_chip->edge_rising & bitmask)
trigger = "edge-rising";
else if (nmk_chip->edge_falling & bitmask)
trigger = "edge-falling";
else
trigger = "edge-undefined";
seq_printf(s, " irq-%d %s%s",
irq, trigger,
irqd_is_wakeup_set(&desc->irq_data)
? " wakeup" : "");
}
seq_printf(s, " irq-%d %s%s",
irq, trigger,
irqd_is_wakeup_set(&desc->irq_data)
? " wakeup" : "");
}
seq_printf(s, "\n");
}
clk_disable(nmk_chip->clk);
}
static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
unsigned i;
unsigned gpio = chip->base;
for (i = 0; i < chip->ngpio; i++, gpio++) {
nmk_gpio_dbg_show_one(s, chip, i, gpio);
seq_printf(s, "\n");
}
}
#else
static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
struct gpio_chip *chip,
unsigned offset, unsigned gpio)
{
}
#define nmk_gpio_dbg_show NULL
#endif
/* This structure is replicated for each GPIO block allocated at probe time */
static struct gpio_chip nmk_gpio_template = {
.request = nmk_gpio_request,
.free = nmk_gpio_free,
.direction_input = nmk_gpio_make_input,
.get = nmk_gpio_get_input,
.direction_output = nmk_gpio_make_output,
@ -1235,7 +1278,9 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
clk_disable(nmk_chip->clk);
#ifdef CONFIG_OF_GPIO
chip->of_node = np;
#endif
ret = gpiochip_add(&nmk_chip->chip);
if (ret)
@ -1280,6 +1325,416 @@ out:
return ret;
}
static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
return npct->soc->ngroups;
}
static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
return npct->soc->groups[selector].name;
}
static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned **pins,
unsigned *num_pins)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
*pins = npct->soc->groups[selector].pins;
*num_pins = npct->soc->groups[selector].npins;
return 0;
}
static struct pinctrl_gpio_range *
nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
int i;
for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
struct pinctrl_gpio_range *range;
range = &npct->soc->gpio_ranges[i];
if (offset >= range->pin_base &&
offset <= (range->pin_base + range->npins - 1))
return range;
}
return NULL;
}
static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
struct pinctrl_gpio_range *range;
struct gpio_chip *chip;
range = nmk_match_gpio_range(pctldev, offset);
if (!range || !range->gc) {
seq_printf(s, "invalid pin offset");
return;
}
chip = range->gc;
nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
}
static struct pinctrl_ops nmk_pinctrl_ops = {
.get_groups_count = nmk_get_groups_cnt,
.get_group_name = nmk_get_group_name,
.get_group_pins = nmk_get_group_pins,
.pin_dbg_show = nmk_pin_dbg_show,
};
static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
return npct->soc->nfunctions;
}
static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned function)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
return npct->soc->functions[function].name;
}
static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
*groups = npct->soc->functions[function].groups;
*num_groups = npct->soc->functions[function].ngroups;
return 0;
}
static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
const struct nmk_pingroup *g;
static unsigned int slpm[NUM_BANKS];
unsigned long flags;
bool glitch;
int ret = -EINVAL;
int i;
g = &npct->soc->groups[group];
if (g->altsetting < 0)
return -EINVAL;
dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
/* Handle this special glitch on altfunction C */
glitch = (g->altsetting == NMK_GPIO_ALT_C);
if (glitch) {
spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
/* Initially don't put any pins to sleep when switching */
memset(slpm, 0xff, sizeof(slpm));
/*
* Then mask the pins that need to be sleeping now when we're
* switching to the ALT C function.
*/
for (i = 0; i < g->npins; i++)
slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
nmk_gpio_glitch_slpm_init(slpm);
}
for (i = 0; i < g->npins; i++) {
struct pinctrl_gpio_range *range;
struct nmk_gpio_chip *nmk_chip;
struct gpio_chip *chip;
unsigned bit;
range = nmk_match_gpio_range(pctldev, g->pins[i]);
if (!range) {
dev_err(npct->dev,
"invalid pin offset %d in group %s at index %d\n",
g->pins[i], g->name, i);
goto out_glitch;
}
if (!range->gc) {
dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
g->pins[i], g->name, i);
goto out_glitch;
}
chip = range->gc;
nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
clk_enable(nmk_chip->clk);
bit = g->pins[i] % NMK_GPIO_PER_CHIP;
/*
* If the pin is switching to altfunc, and there was an
* interrupt installed on it which has been lazy disabled,
* actually mask the interrupt to prevent spurious interrupts
* that would occur while the pin is under control of the
* peripheral. Only SKE does this.
*/
nmk_gpio_disable_lazy_irq(nmk_chip, bit);
__nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch);
clk_disable(nmk_chip->clk);
}
/* When all pins are successfully reconfigured we get here */
ret = 0;
out_glitch:
if (glitch) {
nmk_gpio_glitch_slpm_restore(slpm);
spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
}
return ret;
}
static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
unsigned function, unsigned group)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
const struct nmk_pingroup *g;
g = &npct->soc->groups[group];
if (g->altsetting < 0)
return;
/* Poke out the mux, set the pin to some default state? */
dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
}
int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
struct nmk_gpio_chip *nmk_chip;
struct gpio_chip *chip;
unsigned bit;
if (!range) {
dev_err(npct->dev, "invalid range\n");
return -EINVAL;
}
if (!range->gc) {
dev_err(npct->dev, "missing GPIO chip in range\n");
return -EINVAL;
}
chip = range->gc;
nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
clk_enable(nmk_chip->clk);
bit = offset % NMK_GPIO_PER_CHIP;
/* There is no glitch when converting any pin to GPIO */
__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
clk_disable(nmk_chip->clk);
return 0;
}
void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
/* Set the pin to some default state, GPIO is usually default */
}
static struct pinmux_ops nmk_pinmux_ops = {
.get_functions_count = nmk_pmx_get_funcs_cnt,
.get_function_name = nmk_pmx_get_func_name,
.get_function_groups = nmk_pmx_get_func_groups,
.enable = nmk_pmx_enable,
.disable = nmk_pmx_disable,
.gpio_request_enable = nmk_gpio_request_enable,
.gpio_disable_free = nmk_gpio_disable_free,
};
int nmk_pin_config_get(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *config)
{
/* Not implemented */
return -EINVAL;
}
int nmk_pin_config_set(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long config)
{
static const char *pullnames[] = {
[NMK_GPIO_PULL_NONE] = "none",
[NMK_GPIO_PULL_UP] = "up",
[NMK_GPIO_PULL_DOWN] = "down",
[3] /* illegal */ = "??"
};
static const char *slpmnames[] = {
[NMK_GPIO_SLPM_INPUT] = "input/wakeup",
[NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
};
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
struct nmk_gpio_chip *nmk_chip;
struct pinctrl_gpio_range *range;
struct gpio_chip *chip;
unsigned bit;
/*
* The pin config contains pin number and altfunction fields, here
* we just ignore that part. It's being handled by the framework and
* pinmux callback respectively.
*/
pin_cfg_t cfg = (pin_cfg_t) config;
int pull = PIN_PULL(cfg);
int slpm = PIN_SLPM(cfg);
int output = PIN_DIR(cfg);
int val = PIN_VAL(cfg);
bool lowemi = PIN_LOWEMI(cfg);
bool gpiomode = PIN_GPIOMODE(cfg);
bool sleep = PIN_SLEEPMODE(cfg);
range = nmk_match_gpio_range(pctldev, pin);
if (!range) {
dev_err(npct->dev, "invalid pin offset %d\n", pin);
return -EINVAL;
}
if (!range->gc) {
dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
pin);
return -EINVAL;
}
chip = range->gc;
nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
if (sleep) {
int slpm_pull = PIN_SLPM_PULL(cfg);
int slpm_output = PIN_SLPM_DIR(cfg);
int slpm_val = PIN_SLPM_VAL(cfg);
/* All pins go into GPIO mode at sleep */
gpiomode = true;
/*
* The SLPM_* values are normal values + 1 to allow zero to
* mean "same as normal".
*/
if (slpm_pull)
pull = slpm_pull - 1;
if (slpm_output)
output = slpm_output - 1;
if (slpm_val)
val = slpm_val - 1;
dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
pin,
slpm_pull ? pullnames[pull] : "same",
slpm_output ? (output ? "output" : "input") : "same",
slpm_val ? (val ? "high" : "low") : "same");
}
dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
pin, cfg, pullnames[pull], slpmnames[slpm],
output ? "output " : "input",
output ? (val ? "high" : "low") : "",
lowemi ? "on" : "off" );
clk_enable(nmk_chip->clk);
bit = pin % NMK_GPIO_PER_CHIP;
if (gpiomode)
/* No glitch when going to GPIO mode */
__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
if (output)
__nmk_gpio_make_output(nmk_chip, bit, val);
else {
__nmk_gpio_make_input(nmk_chip, bit);
__nmk_gpio_set_pull(nmk_chip, bit, pull);
}
/* TODO: isn't this only applicable on output pins? */
__nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
__nmk_gpio_set_slpm(nmk_chip, bit, slpm);
clk_disable(nmk_chip->clk);
return 0;
}
static struct pinconf_ops nmk_pinconf_ops = {
.pin_config_get = nmk_pin_config_get,
.pin_config_set = nmk_pin_config_set,
};
static struct pinctrl_desc nmk_pinctrl_desc = {
.name = "pinctrl-nomadik",
.pctlops = &nmk_pinctrl_ops,
.pmxops = &nmk_pinmux_ops,
.confops = &nmk_pinconf_ops,
.owner = THIS_MODULE,
};
static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
{
const struct platform_device_id *platid = platform_get_device_id(pdev);
struct nmk_pinctrl *npct;
int i;
npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
if (!npct)
return -ENOMEM;
/* Poke in other ASIC variants here */
if (platid->driver_data == PINCTRL_NMK_DB8500)
nmk_pinctrl_db8500_init(&npct->soc);
/*
* We need all the GPIO drivers to probe FIRST, or we will not be able
* to obtain references to the struct gpio_chip * for them, and we
* need this to proceed.
*/
for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
if (!nmk_gpio_chips[i]) {
dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
devm_kfree(&pdev->dev, npct);
return -EPROBE_DEFER;
}
npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
}
nmk_pinctrl_desc.pins = npct->soc->pins;
nmk_pinctrl_desc.npins = npct->soc->npins;
npct->dev = &pdev->dev;
npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
if (!npct->pctl) {
dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
return -EINVAL;
}
/* We will handle a range of GPIO pins */
for (i = 0; i < npct->soc->gpio_num_ranges; i++)
pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
platform_set_drvdata(pdev, npct);
dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
return 0;
}
static const struct of_device_id nmk_gpio_match[] = {
{ .compatible = "st,nomadik-gpio", },
{}
@ -1294,9 +1749,28 @@ static struct platform_driver nmk_gpio_driver = {
.probe = nmk_gpio_probe,
};
static const struct platform_device_id nmk_pinctrl_id[] = {
{ "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
{ "pinctrl-db8500", PINCTRL_NMK_DB8500 },
};
static struct platform_driver nmk_pinctrl_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "pinctrl-nomadik",
},
.probe = nmk_pinctrl_probe,
.id_table = nmk_pinctrl_id,
};
static int __init nmk_gpio_init(void)
{
return platform_driver_register(&nmk_gpio_driver);
int ret;
ret = platform_driver_register(&nmk_gpio_driver);
if (ret)
return ret;
return platform_driver_register(&nmk_pinctrl_driver);
}
core_initcall(nmk_gpio_init);

77
drivers/pinctrl/pinctrl-nomadik.h Normal file
View file

@ -0,0 +1,77 @@
#ifndef PINCTRL_PINCTRL_NOMADIK_H
#define PINCTRL_PINCTRL_NOMADIK_H
#include <plat/gpio-nomadik.h>
/* Package definitions */
#define PINCTRL_NMK_STN8815 0
#define PINCTRL_NMK_DB8500 1
/**
* struct nmk_function - Nomadik pinctrl mux function
* @name: The name of the function, exported to pinctrl core.
* @groups: An array of pin groups that may select this function.
* @ngroups: The number of entries in @groups.
*/
struct nmk_function {
const char *name;
const char * const *groups;
unsigned ngroups;
};
/**
* struct nmk_pingroup - describes a Nomadik pin group
* @name: the name of this specific pin group
* @pins: an array of discrete physical pins used in this group, taken
* from the driver-local pin enumeration space
* @num_pins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
* @altsetting: the altsetting to apply to all pins in this group to
* configure them to be used by a function
*/
struct nmk_pingroup {
const char *name;
const unsigned int *pins;
const unsigned npins;
int altsetting;
};
/**
* struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
* @gpio_ranges: An array of GPIO ranges for this SoC
* @gpio_num_ranges: The number of GPIO ranges for this SoC
* @pins: An array describing all pins the pin controller affects.
* All pins which are also GPIOs must be listed first within the
* array, and be numbered identically to the GPIO controller's
* numbering.
* @npins: The number of entries in @pins.
* @functions: The functions supported on this SoC.
* @nfunction: The number of entries in @functions.
* @groups: An array describing all pin groups the pin SoC supports.
* @ngroups: The number of entries in @groups.
*/
struct nmk_pinctrl_soc_data {
struct pinctrl_gpio_range *gpio_ranges;
unsigned gpio_num_ranges;
const struct pinctrl_pin_desc *pins;
unsigned npins;
const struct nmk_function *functions;
unsigned nfunctions;
const struct nmk_pingroup *groups;
unsigned ngroups;
};
#ifdef CONFIG_PINCTRL_DB8500
void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
#else
static inline void
nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
{
}
#endif
#endif /* PINCTRL_PINCTRL_NOMADIK_H */

13
include/linux/pinctrl/pinctrl-state.h
View file

@ -2,5 +2,18 @@
* Standard pin control state definitions
*/
/**
* @PINCTRL_STATE_DEFAULT: the state the pinctrl handle shall be put
* into as default, usually this means the pins are up and ready to
* be used by the device driver. This state is commonly used by
* hogs to configure muxing and pins at boot.
* @PINCTRL_STATE_IDLE: the state the pinctrl handle shall be put into
* when the pins are idle. Could typically be set from a
* pm_runtime_suspend() operation.
* @PINCTRL_STATE_SLEEP: the state the pinctrl handle shall be put into
* when the pins are sleeping. Could typically be set from a
* common suspend() function.
*/
#define PINCTRL_STATE_DEFAULT "default"
#define PINCTRL_STATE_IDLE "idle"
#define PINCTRL_STATE_SLEEP "sleep"