KVM: PPC: Book3S HV: Add new state for transactional memory
Add new state for transactional memory (TM) to kvm_vcpu_arch. Also add asm-offset bits that are going to be required. This also moves the existing TFHAR, TFIAR and TEXASR SPRs into a CONFIG_PPC_TRANSACTIONAL_MEM section. This requires some code changes to ensure we still compile with CONFIG_PPC_TRANSACTIONAL_MEM=N. Much of the added the added #ifdefs are removed in a later patch when the bulk of the TM code is added. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Paul Mackerras <paulus@samba.org> [agraf: fix merge conflict] Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -475,9 +475,6 @@ struct kvm_vcpu_arch {
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ulong ppr;
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ulong pspb;
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ulong fscr;
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ulong tfhar;
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ulong tfiar;
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ulong texasr;
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ulong ebbhr;
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ulong ebbrr;
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ulong bescr;
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@ -526,6 +523,27 @@ struct kvm_vcpu_arch {
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u64 siar;
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u64 sdar;
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u64 sier;
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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u64 tfhar;
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u64 texasr;
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u64 tfiar;
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u32 cr_tm;
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u64 lr_tm;
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u64 ctr_tm;
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u64 amr_tm;
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u64 ppr_tm;
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u64 dscr_tm;
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u64 tar_tm;
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ulong gpr_tm[32];
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struct thread_fp_state fp_tm;
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struct thread_vr_state vr_tm;
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u32 vrsave_tm; /* also USPRG0 */
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#endif
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#ifdef CONFIG_KVM_EXIT_TIMING
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struct mutex exit_timing_lock;
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@ -521,9 +521,6 @@ int main(void)
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DEFINE(VCPU_PPR, offsetof(struct kvm_vcpu, arch.ppr));
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DEFINE(VCPU_FSCR, offsetof(struct kvm_vcpu, arch.fscr));
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DEFINE(VCPU_PSPB, offsetof(struct kvm_vcpu, arch.pspb));
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DEFINE(VCPU_TFHAR, offsetof(struct kvm_vcpu, arch.tfhar));
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DEFINE(VCPU_TFIAR, offsetof(struct kvm_vcpu, arch.tfiar));
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DEFINE(VCPU_TEXASR, offsetof(struct kvm_vcpu, arch.texasr));
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DEFINE(VCPU_EBBHR, offsetof(struct kvm_vcpu, arch.ebbhr));
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DEFINE(VCPU_EBBRR, offsetof(struct kvm_vcpu, arch.ebbrr));
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DEFINE(VCPU_BESCR, offsetof(struct kvm_vcpu, arch.bescr));
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@ -545,6 +542,22 @@ int main(void)
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DEFINE(VCPU_SLB_E, offsetof(struct kvmppc_slb, orige));
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DEFINE(VCPU_SLB_V, offsetof(struct kvmppc_slb, origv));
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DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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DEFINE(VCPU_TFHAR, offsetof(struct kvm_vcpu, arch.tfhar));
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DEFINE(VCPU_TFIAR, offsetof(struct kvm_vcpu, arch.tfiar));
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DEFINE(VCPU_TEXASR, offsetof(struct kvm_vcpu, arch.texasr));
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DEFINE(VCPU_GPR_TM, offsetof(struct kvm_vcpu, arch.gpr_tm));
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DEFINE(VCPU_FPRS_TM, offsetof(struct kvm_vcpu, arch.fp_tm.fpr));
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DEFINE(VCPU_VRS_TM, offsetof(struct kvm_vcpu, arch.vr_tm.vr));
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DEFINE(VCPU_VRSAVE_TM, offsetof(struct kvm_vcpu, arch.vrsave_tm));
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DEFINE(VCPU_CR_TM, offsetof(struct kvm_vcpu, arch.cr_tm));
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DEFINE(VCPU_LR_TM, offsetof(struct kvm_vcpu, arch.lr_tm));
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DEFINE(VCPU_CTR_TM, offsetof(struct kvm_vcpu, arch.ctr_tm));
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DEFINE(VCPU_AMR_TM, offsetof(struct kvm_vcpu, arch.amr_tm));
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DEFINE(VCPU_PPR_TM, offsetof(struct kvm_vcpu, arch.ppr_tm));
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DEFINE(VCPU_DSCR_TM, offsetof(struct kvm_vcpu, arch.dscr_tm));
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DEFINE(VCPU_TAR_TM, offsetof(struct kvm_vcpu, arch.tar_tm));
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
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@ -875,6 +875,7 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
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case KVM_REG_PPC_IAMR:
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*val = get_reg_val(id, vcpu->arch.iamr);
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break;
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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case KVM_REG_PPC_TFHAR:
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*val = get_reg_val(id, vcpu->arch.tfhar);
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break;
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@ -884,6 +885,7 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
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case KVM_REG_PPC_TEXASR:
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*val = get_reg_val(id, vcpu->arch.texasr);
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break;
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#endif
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case KVM_REG_PPC_FSCR:
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*val = get_reg_val(id, vcpu->arch.fscr);
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break;
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@ -1033,6 +1035,7 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
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case KVM_REG_PPC_IAMR:
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vcpu->arch.iamr = set_reg_val(id, *val);
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break;
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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case KVM_REG_PPC_TFHAR:
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vcpu->arch.tfhar = set_reg_val(id, *val);
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break;
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@ -1042,6 +1045,7 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
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case KVM_REG_PPC_TEXASR:
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vcpu->arch.texasr = set_reg_val(id, *val);
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break;
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#endif
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case KVM_REG_PPC_FSCR:
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vcpu->arch.fscr = set_reg_val(id, *val);
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break;
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@ -701,13 +701,15 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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ld r6, VCPU_VTB(r4)
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mtspr SPRN_IC, r5
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mtspr SPRN_VTB, r6
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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ld r5, VCPU_TFHAR(r4)
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ld r6, VCPU_TFIAR(r4)
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ld r7, VCPU_TEXASR(r4)
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ld r8, VCPU_EBBHR(r4)
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mtspr SPRN_TFHAR, r5
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mtspr SPRN_TFIAR, r6
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mtspr SPRN_TEXASR, r7
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#endif
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ld r8, VCPU_EBBHR(r4)
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mtspr SPRN_EBBHR, r8
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ld r5, VCPU_EBBRR(r4)
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ld r6, VCPU_BESCR(r4)
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@ -1118,13 +1120,15 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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std r5, VCPU_IC(r9)
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std r6, VCPU_VTB(r9)
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std r7, VCPU_TAR(r9)
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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mfspr r5, SPRN_TFHAR
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mfspr r6, SPRN_TFIAR
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mfspr r7, SPRN_TEXASR
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mfspr r8, SPRN_EBBHR
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std r5, VCPU_TFHAR(r9)
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std r6, VCPU_TFIAR(r9)
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std r7, VCPU_TEXASR(r9)
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#endif
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mfspr r8, SPRN_EBBHR
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std r8, VCPU_EBBHR(r9)
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mfspr r5, SPRN_EBBRR
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mfspr r6, SPRN_BESCR
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@ -1497,6 +1501,73 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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1: addi r8,r8,16
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.endr
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/* Save DEC */
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mfspr r5,SPRN_DEC
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mftb r6
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extsw r5,r5
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add r5,r5,r6
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std r5,VCPU_DEC_EXPIRES(r9)
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BEGIN_FTR_SECTION
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b 8f
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END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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/* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
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mfmsr r8
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li r0, 1
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rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
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mtmsrd r8
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/* Save POWER8-specific registers */
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mfspr r5, SPRN_IAMR
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mfspr r6, SPRN_PSPB
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mfspr r7, SPRN_FSCR
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std r5, VCPU_IAMR(r9)
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stw r6, VCPU_PSPB(r9)
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std r7, VCPU_FSCR(r9)
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mfspr r5, SPRN_IC
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mfspr r6, SPRN_VTB
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mfspr r7, SPRN_TAR
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std r5, VCPU_IC(r9)
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std r6, VCPU_VTB(r9)
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std r7, VCPU_TAR(r9)
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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mfspr r5, SPRN_TFHAR
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mfspr r6, SPRN_TFIAR
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mfspr r7, SPRN_TEXASR
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std r5, VCPU_TFHAR(r9)
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std r6, VCPU_TFIAR(r9)
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std r7, VCPU_TEXASR(r9)
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#endif
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mfspr r8, SPRN_EBBHR
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std r8, VCPU_EBBHR(r9)
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mfspr r5, SPRN_EBBRR
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mfspr r6, SPRN_BESCR
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mfspr r7, SPRN_CSIGR
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mfspr r8, SPRN_TACR
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std r5, VCPU_EBBRR(r9)
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std r6, VCPU_BESCR(r9)
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std r7, VCPU_CSIGR(r9)
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std r8, VCPU_TACR(r9)
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mfspr r5, SPRN_TCSCR
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mfspr r6, SPRN_ACOP
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mfspr r7, SPRN_PID
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mfspr r8, SPRN_WORT
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std r5, VCPU_TCSCR(r9)
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std r6, VCPU_ACOP(r9)
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stw r7, VCPU_GUEST_PID(r9)
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std r8, VCPU_WORT(r9)
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8:
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/* Save and reset AMR and UAMOR before turning on the MMU */
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BEGIN_FTR_SECTION
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mfspr r5,SPRN_AMR
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mfspr r6,SPRN_UAMOR
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std r5,VCPU_AMR(r9)
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std r6,VCPU_UAMOR(r9)
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li r6,0
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mtspr SPRN_AMR,r6
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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/* Unset guest mode */
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li r0, KVM_GUEST_MODE_NONE
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stb r0, HSTATE_IN_GUEST(r13)
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