KVM: MMU: Add EPT support
Enable kvm_set_spte() to generate EPT entries. Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
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@ -152,6 +152,12 @@ static struct kmem_cache *mmu_page_header_cache;
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static u64 __read_mostly shadow_trap_nonpresent_pte;
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static u64 __read_mostly shadow_notrap_nonpresent_pte;
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static u64 __read_mostly shadow_base_present_pte;
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static u64 __read_mostly shadow_nx_mask;
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static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
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static u64 __read_mostly shadow_user_mask;
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static u64 __read_mostly shadow_accessed_mask;
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static u64 __read_mostly shadow_dirty_mask;
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void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
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{
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@ -160,6 +166,23 @@ void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
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void kvm_mmu_set_base_ptes(u64 base_pte)
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{
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shadow_base_present_pte = base_pte;
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
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void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
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u64 dirty_mask, u64 nx_mask, u64 x_mask)
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{
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shadow_user_mask = user_mask;
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shadow_accessed_mask = accessed_mask;
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shadow_dirty_mask = dirty_mask;
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shadow_nx_mask = nx_mask;
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shadow_x_mask = x_mask;
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
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static int is_write_protection(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.cr0 & X86_CR0_WP;
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@ -198,7 +221,7 @@ static int is_writeble_pte(unsigned long pte)
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static int is_dirty_pte(unsigned long pte)
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{
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return pte & PT_DIRTY_MASK;
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return pte & shadow_dirty_mask;
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}
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static int is_rmap_pte(u64 pte)
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@ -513,7 +536,7 @@ static void rmap_remove(struct kvm *kvm, u64 *spte)
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return;
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sp = page_header(__pa(spte));
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pfn = spte_to_pfn(*spte);
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if (*spte & PT_ACCESSED_MASK)
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if (*spte & shadow_accessed_mask)
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kvm_set_pfn_accessed(pfn);
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if (is_writeble_pte(*spte))
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kvm_release_pfn_dirty(pfn);
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@ -1039,17 +1062,17 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
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* whether the guest actually used the pte (in order to detect
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* demand paging).
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*/
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spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
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spte = shadow_base_present_pte | shadow_dirty_mask;
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if (!speculative)
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pte_access |= PT_ACCESSED_MASK;
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if (!dirty)
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pte_access &= ~ACC_WRITE_MASK;
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if (!(pte_access & ACC_EXEC_MASK))
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spte |= PT64_NX_MASK;
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spte |= PT_PRESENT_MASK;
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if (pte_access & ACC_EXEC_MASK)
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spte |= shadow_x_mask;
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else
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spte |= shadow_nx_mask;
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if (pte_access & ACC_USER_MASK)
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spte |= PT_USER_MASK;
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spte |= shadow_user_mask;
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if (largepage)
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spte |= PT_PAGE_SIZE_MASK;
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@ -1155,7 +1178,7 @@ static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
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}
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table[index] = __pa(new_table->spt) | PT_PRESENT_MASK
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| PT_WRITABLE_MASK | PT_USER_MASK;
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| PT_WRITABLE_MASK | shadow_user_mask;
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}
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table_addr = table[index] & PT64_BASE_ADDR_MASK;
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}
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@ -1599,7 +1622,7 @@ static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
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{
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u64 *spte = vcpu->arch.last_pte_updated;
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return !!(spte && (*spte & PT_ACCESSED_MASK));
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return !!(spte && (*spte & shadow_accessed_mask));
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}
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static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
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@ -2417,6 +2417,9 @@ int kvm_arch_init(void *opaque)
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kvm_x86_ops = ops;
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kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
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kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
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kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
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PT_DIRTY_MASK, PT64_NX_MASK, 0);
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return 0;
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out:
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@ -434,6 +434,9 @@ void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
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int kvm_mmu_create(struct kvm_vcpu *vcpu);
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int kvm_mmu_setup(struct kvm_vcpu *vcpu);
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void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte);
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void kvm_mmu_set_base_ptes(u64 base_pte);
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void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
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u64 dirty_mask, u64 nx_mask, u64 x_mask);
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int kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
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void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot);
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