watchdog: w83627hf: Add support for W83697HF and W83697UG
Major difference is that the watchdog control and counter registers are different on both chips. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Guenter Roeck
Wim Van Sebroeck
parent
962c04f54e
commit
7b6d0b6ad4
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@ -902,6 +902,8 @@ config W83627HF_WDT
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W83637HF
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W83667HG/HG-B
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W83687THF
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W83697HF
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W83697UG
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NCT6775
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NCT6776
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NCT6779
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@ -45,10 +45,12 @@
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#define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */
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static int wdt_io;
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static int cr_wdt_timeout; /* WDT timeout register */
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static int cr_wdt_control; /* WDT control register */
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enum chips { w83627hf, w83627s, w83637hf, w83627thf, w83687thf,
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w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p, w83667hg_b,
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nct6775, nct6776, nct6779 };
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enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf,
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w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p,
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w83667hg_b, nct6775, nct6776, nct6779 };
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static int timeout; /* in seconds */
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module_param(timeout, int, 0);
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@ -75,6 +77,8 @@ MODULE_PARM_DESC(nowayout,
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#define W83627HF_ID 0x52
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#define W83627S_ID 0x59
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#define W83697HF_ID 0x60
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#define W83697UG_ID 0x68
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#define W83637HF_ID 0x70
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#define W83627THF_ID 0x82
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#define W83687THF_ID 0x85
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@ -88,6 +92,12 @@ MODULE_PARM_DESC(nowayout,
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#define NCT6776_ID 0xc3
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#define NCT6779_ID 0xc5
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#define W83627HF_WDT_TIMEOUT 0xf6
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#define W83697HF_WDT_TIMEOUT 0xf4
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#define W83627HF_WDT_CONTROL 0xf5
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#define W83697HF_WDT_CONTROL 0xf3
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static void superio_outb(int reg, int val)
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{
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outb(reg, WDT_EFER);
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@ -144,6 +154,17 @@ static int w83627hf_init(struct watchdog_device *wdog, enum chips chip)
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t = superio_inb(0x2B) & ~0x10;
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superio_outb(0x2B, t); /* set GPIO24 to WDT0 */
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break;
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case w83697hf:
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/* Set pin 119 to WDTO# mode (= CR29, WDT0) */
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t = superio_inb(0x29) & ~0x60;
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t |= 0x20;
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superio_outb(0x29, t);
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break;
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case w83697ug:
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/* Set pin 118 to WDTO# mode */
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t = superio_inb(0x2b) & ~0x04;
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superio_outb(0x2b, t);
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break;
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case w83627thf:
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t = (superio_inb(0x2B) & ~0x08) | 0x04;
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superio_outb(0x2B, t); /* set GPIO3 to WDT0 */
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@ -152,10 +173,10 @@ static int w83627hf_init(struct watchdog_device *wdog, enum chips chip)
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case w83627dhg_p:
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t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */
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superio_outb(0x2D, t); /* set GPIO5 to WDT0 */
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t = superio_inb(0xF5);
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t = superio_inb(cr_wdt_control);
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t |= 0x02; /* enable the WDTO# output low pulse
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* to the KBRST# pin */
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superio_outb(0xF5, t);
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superio_outb(cr_wdt_control, t);
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break;
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case w83637hf:
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break;
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@ -176,25 +197,25 @@ static int w83627hf_init(struct watchdog_device *wdog, enum chips chip)
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* Don't touch its configuration, and hope the BIOS
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* does the right thing.
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*/
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t = superio_inb(0xF5);
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t = superio_inb(cr_wdt_control);
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t |= 0x02; /* enable the WDTO# output low pulse
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* to the KBRST# pin */
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superio_outb(0xF5, t);
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superio_outb(cr_wdt_control, t);
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break;
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default:
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break;
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}
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t = superio_inb(0xF6);
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t = superio_inb(cr_wdt_timeout);
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if (t != 0) {
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pr_info("Watchdog already running. Resetting timeout to %d sec\n",
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wdog->timeout);
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superio_outb(0xF6, wdog->timeout);
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superio_outb(cr_wdt_timeout, wdog->timeout);
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}
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/* set second mode & disable keyboard turning off watchdog */
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t = superio_inb(0xF5) & ~0x0C;
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superio_outb(0xF5, t);
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t = superio_inb(cr_wdt_control) & ~0x0C;
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superio_outb(cr_wdt_control, t);
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/* disable keyboard & mouse turning off watchdog */
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t = superio_inb(0xF7) & ~0xC0;
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@ -214,7 +235,7 @@ static int wdt_set_time(unsigned int timeout)
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return ret;
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superio_select(W83627HF_LD_WDT);
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superio_outb(0xF6, timeout);
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superio_outb(cr_wdt_timeout, timeout);
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superio_exit();
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return 0;
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@ -247,7 +268,7 @@ static unsigned int wdt_get_time(struct watchdog_device *wdog)
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return 0;
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superio_select(W83627HF_LD_WDT);
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timeleft = superio_inb(0xF6);
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timeleft = superio_inb(cr_wdt_timeout);
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superio_exit();
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return timeleft;
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@ -304,6 +325,9 @@ static int wdt_find(int addr)
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u8 val;
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int ret;
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cr_wdt_timeout = W83627HF_WDT_TIMEOUT;
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cr_wdt_control = W83627HF_WDT_CONTROL;
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ret = superio_enter();
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if (ret)
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return ret;
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@ -316,6 +340,16 @@ static int wdt_find(int addr)
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case W83627S_ID:
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ret = w83627s;
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break;
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case W83697HF_ID:
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ret = w83697hf;
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cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
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cr_wdt_control = W83697HF_WDT_CONTROL;
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break;
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case W83697UG_ID:
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ret = w83697ug;
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cr_wdt_timeout = W83697HF_WDT_TIMEOUT;
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cr_wdt_control = W83697HF_WDT_CONTROL;
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break;
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case W83637HF_ID:
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ret = w83637hf;
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break;
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@ -371,6 +405,8 @@ static int __init wdt_init(void)
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const char * const chip_name[] = {
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"W83627HF",
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"W83627S",
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"W83697HF",
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"W83697UG",
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"W83637HF",
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"W83627THF",
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"W83687THF",
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