ixgbe: Lock RSS seed, move rx_buf_len to the rx_ring
This locks the seed down so loading/unloading the driver will present predictable hashing from RSS. Also move the rx_buf_len out of the adapter struct, and into the Rx ring struct. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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e01c31a5f7
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7c6e0a436d
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@ -166,6 +166,7 @@ struct ixgbe_ring {
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char name[IFNAMSIZ + 5];
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u16 work_limit; /* max work per interrupt */
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u16 rx_buf_len;
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};
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#define RING_F_VMDQ 1
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@ -228,7 +229,6 @@ struct ixgbe_adapter {
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struct timer_list watchdog_timer;
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struct vlan_group *vlgrp;
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u16 bd_number;
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u16 rx_buf_len;
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struct work_struct reset_task;
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struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
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char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
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@ -474,15 +474,15 @@ static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
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* @adapter: address of board private structure
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**/
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static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *rx_ring,
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int cleaned_count)
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struct ixgbe_ring *rx_ring,
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int cleaned_count)
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{
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struct net_device *netdev = adapter->netdev;
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struct pci_dev *pdev = adapter->pdev;
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union ixgbe_adv_rx_desc *rx_desc;
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struct ixgbe_rx_buffer *bi;
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unsigned int i;
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unsigned int bufsz = adapter->rx_buf_len + NET_IP_ALIGN;
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unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
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i = rx_ring->next_to_use;
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bi = &rx_ring->rx_buffer_info[i];
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@ -498,8 +498,8 @@ static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
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goto no_buffers;
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}
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bi->page_dma = pci_map_page(pdev, bi->page, 0,
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PAGE_SIZE,
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PCI_DMA_FROMDEVICE);
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PAGE_SIZE,
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PCI_DMA_FROMDEVICE);
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}
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if (!bi->skb) {
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@ -535,6 +535,7 @@ static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
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i = 0;
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bi = &rx_ring->rx_buffer_info[i];
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}
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no_buffers:
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if (rx_ring->next_to_use != i) {
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rx_ring->next_to_use = i;
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@ -552,9 +553,19 @@ no_buffers:
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}
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}
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static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
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{
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return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
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}
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static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
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{
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return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
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}
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static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *rx_ring,
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int *work_done, int work_to_do)
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struct ixgbe_ring *rx_ring,
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int *work_done, int work_to_do)
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{
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struct net_device *netdev = adapter->netdev;
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struct pci_dev *pdev = adapter->pdev;
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@ -562,36 +573,35 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
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struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
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struct sk_buff *skb;
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unsigned int i;
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u32 upper_len, len, staterr;
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u32 len, staterr;
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u16 hdr_info;
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bool cleaned = false;
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int cleaned_count = 0;
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unsigned int total_rx_bytes = 0, total_rx_packets = 0;
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i = rx_ring->next_to_clean;
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upper_len = 0;
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rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
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staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
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rx_buffer_info = &rx_ring->rx_buffer_info[i];
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while (staterr & IXGBE_RXD_STAT_DD) {
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u32 upper_len = 0;
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if (*work_done >= work_to_do)
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break;
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(*work_done)++;
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if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
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hdr_info =
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le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info);
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len =
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((hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
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IXGBE_RXDADV_HDRBUFLEN_SHIFT);
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hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
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len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
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IXGBE_RXDADV_HDRBUFLEN_SHIFT;
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if (hdr_info & IXGBE_RXDADV_SPH)
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adapter->rx_hdr_split++;
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if (len > IXGBE_RX_HDR_SIZE)
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len = IXGBE_RX_HDR_SIZE;
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upper_len = le16_to_cpu(rx_desc->wb.upper.length);
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} else
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} else {
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len = le16_to_cpu(rx_desc->wb.upper.length);
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}
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cleaned = true;
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skb = rx_buffer_info->skb;
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@ -600,8 +610,8 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
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if (len && !skb_shinfo(skb)->nr_frags) {
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pci_unmap_single(pdev, rx_buffer_info->dma,
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adapter->rx_buf_len + NET_IP_ALIGN,
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PCI_DMA_FROMDEVICE);
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rx_ring->rx_buf_len + NET_IP_ALIGN,
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PCI_DMA_FROMDEVICE);
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skb_put(skb, len);
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}
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@ -1415,7 +1425,7 @@ static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
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union ixgbe_adv_rx_desc *rx_desc = priv;
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/* Verify that this is a valid IPv4 TCP packet */
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if (!(rx_desc->wb.lower.lo_dword.pkt_info &
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if (!(ixgbe_get_pkt_info(rx_desc) &
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(IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP)))
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return -1;
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@ -1442,10 +1452,13 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
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int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
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int i, j;
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u32 rdlen, rxctrl, rxcsum;
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u32 random[10];
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static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
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0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
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0x6A3E67EA, 0x14364D17, 0x3BED200D};
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u32 fctrl, hlreg0;
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u32 pages;
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u32 reta = 0, mrqc, srrctl;
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int rx_buf_len;
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/* Decide whether to use packet split mode or not */
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if (netdev->mtu > ETH_DATA_LEN)
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@ -1455,12 +1468,12 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
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/* Set the RX buffer length according to the mode */
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if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
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adapter->rx_buf_len = IXGBE_RX_HDR_SIZE;
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rx_buf_len = IXGBE_RX_HDR_SIZE;
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} else {
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if (netdev->mtu <= ETH_DATA_LEN)
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adapter->rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
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rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
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else
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adapter->rx_buf_len = ALIGN(max_frame, 1024);
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rx_buf_len = ALIGN(max_frame, 1024);
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}
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fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
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@ -1490,12 +1503,11 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
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} else {
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srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
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if (adapter->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
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if (rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
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srrctl |=
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IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
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else
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srrctl |=
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adapter->rx_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
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srrctl |= rx_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
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}
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(0), srrctl);
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@ -1508,13 +1520,15 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
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* the Base and Length of the Rx Descriptor Ring */
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for (i = 0; i < adapter->num_rx_queues; i++) {
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rdba = adapter->rx_ring[i].dma;
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IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i), (rdba & DMA_32BIT_MASK));
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IXGBE_WRITE_REG(hw, IXGBE_RDBAH(i), (rdba >> 32));
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IXGBE_WRITE_REG(hw, IXGBE_RDLEN(i), rdlen);
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IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
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adapter->rx_ring[i].head = IXGBE_RDH(i);
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adapter->rx_ring[i].tail = IXGBE_RDT(i);
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j = adapter->rx_ring[i].reg_idx;
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IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
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IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
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IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
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IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
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IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
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adapter->rx_ring[i].head = IXGBE_RDH(j);
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adapter->rx_ring[i].tail = IXGBE_RDT(j);
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adapter->rx_ring[i].rx_buf_len = rx_buf_len;
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}
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/* Intitial LRO Settings */
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@ -1541,22 +1555,20 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
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}
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/* Fill out hash function seeds */
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/* XXX use a random constant here to glue certain flows */
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get_random_bytes(&random[0], 40);
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for (i = 0; i < 10; i++)
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IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), random[i]);
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IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
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mrqc = IXGBE_MRQC_RSSEN
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/* Perform hash on these packet types */
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| IXGBE_MRQC_RSS_FIELD_IPV4
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| IXGBE_MRQC_RSS_FIELD_IPV4_TCP
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| IXGBE_MRQC_RSS_FIELD_IPV4_UDP
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| IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
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| IXGBE_MRQC_RSS_FIELD_IPV6_EX
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| IXGBE_MRQC_RSS_FIELD_IPV6
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| IXGBE_MRQC_RSS_FIELD_IPV6_TCP
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| IXGBE_MRQC_RSS_FIELD_IPV6_UDP
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| IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
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| IXGBE_MRQC_RSS_FIELD_IPV4
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| IXGBE_MRQC_RSS_FIELD_IPV4_TCP
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| IXGBE_MRQC_RSS_FIELD_IPV4_UDP
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| IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
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| IXGBE_MRQC_RSS_FIELD_IPV6_EX
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| IXGBE_MRQC_RSS_FIELD_IPV6
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| IXGBE_MRQC_RSS_FIELD_IPV6_TCP
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| IXGBE_MRQC_RSS_FIELD_IPV6_UDP
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| IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
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IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
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}
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@ -1926,7 +1938,7 @@ static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
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rx_buffer_info = &rx_ring->rx_buffer_info[i];
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if (rx_buffer_info->dma) {
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pci_unmap_single(pdev, rx_buffer_info->dma,
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adapter->rx_buf_len,
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rx_ring->rx_buf_len,
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PCI_DMA_FROMDEVICE);
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rx_buffer_info->dma = 0;
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}
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@ -1049,9 +1049,12 @@ union ixgbe_adv_rx_desc {
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} read;
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struct {
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struct {
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struct {
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__le16 pkt_info; /* RSS type, Packet type */
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__le16 hdr_info; /* Split Header, header len */
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union {
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__le32 data;
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struct {
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__le16 pkt_info; /* RSS type, Packet type */
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__le16 hdr_info; /* Split Header, header len */
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} hs_rss;
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} lo_dword;
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union {
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__le32 rss; /* RSS Hash */
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