clk: exynos3250: Add cpu clock configuration data and instaniate cpu clock
This patch add CPU clock configuration data and instantiate the CPU clock type for Exynos3250 to support Samsung specific cpu-clock type. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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@ -19,6 +19,7 @@
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#include <dt-bindings/clock/exynos3250.h>
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#include <dt-bindings/clock/exynos3250.h>
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#include "clk.h"
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#include "clk.h"
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#include "clk-cpu.h"
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#include "clk-pll.h"
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#include "clk-pll.h"
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#define SRC_LEFTBUS 0x4200
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#define SRC_LEFTBUS 0x4200
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@ -319,8 +320,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
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MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
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MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
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SRC_CPU, 24, 1),
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SRC_CPU, 24, 1),
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MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
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MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
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MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
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MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
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MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
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CLK_SET_RATE_PARENT, 0),
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MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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CLK_SET_RATE_PARENT, 0),
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};
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};
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static struct samsung_div_clock div_clks[] __initdata = {
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static struct samsung_div_clock div_clks[] __initdata = {
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@ -772,6 +775,26 @@ static struct samsung_cmu_info cmu_info __initdata = {
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.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
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.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
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};
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};
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#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
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(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
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((corem) << 4))
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#define E3250_CPU_DIV1(hpm, copy) \
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(((hpm) << 4) | ((copy) << 0))
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static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
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{ 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
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{ 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
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{ 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
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{ 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
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{ 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
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{ 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
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{ 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
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{ 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
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{ 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
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{ 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
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{ 0 },
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};
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static void __init exynos3250_cmu_init(struct device_node *np)
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static void __init exynos3250_cmu_init(struct device_node *np)
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{
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{
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struct samsung_clk_provider *ctx;
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struct samsung_clk_provider *ctx;
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@ -780,6 +803,11 @@ static void __init exynos3250_cmu_init(struct device_node *np)
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if (!ctx)
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if (!ctx)
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return;
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return;
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_core_p[0], mout_core_p[1], 0x14200,
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e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
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CLK_CPU_HAS_DIV1);
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exynos3_core_down_clock(ctx->reg_base);
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exynos3_core_down_clock(ctx->reg_base);
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}
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}
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CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
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CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
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@ -31,6 +31,7 @@
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#define CLK_FOUT_VPLL 4
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#define CLK_FOUT_VPLL 4
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#define CLK_FOUT_UPLL 5
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#define CLK_FOUT_UPLL 5
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#define CLK_FOUT_MPLL 6
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#define CLK_FOUT_MPLL 6
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#define CLK_ARM_CLK 7
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/* Muxes */
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/* Muxes */
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#define CLK_MOUT_MPLL_USER_L 16
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#define CLK_MOUT_MPLL_USER_L 16
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