mfd: intel_soc_pmic: Crystal Cove support
This patch provides chip-specific support for Crystal Cove. Crystal Cove is the PMIC in Baytrail-T platform. Also adds Intel SoC PMIC support to the build files. Signed-off-by: Yang, Bin <bin.yang@intel.com> Signed-off-by: Zhu, Lejun <lejun.zhu@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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@ -253,6 +253,18 @@ config LPC_SCH
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LPC bridge function of the Intel SCH provides support for
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System Management Bus and General Purpose I/O.
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config INTEL_SOC_PMIC
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bool "Support for Intel Atom SoC PMIC"
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depends on I2C=y
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select MFD_CORE
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select REGMAP_I2C
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select REGMAP_IRQ
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help
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Select this option to enable support for the PMIC device
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on some Intel SoC systems. The PMIC provides ADC, GPIO,
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thermal, charger and related power management functions
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on these systems.
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config MFD_INTEL_MSIC
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bool "Intel MSIC"
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depends on INTEL_SCU_IPC
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@ -169,3 +169,6 @@ obj-$(CONFIG_MFD_AS3711) += as3711.o
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obj-$(CONFIG_MFD_AS3722) += as3722.o
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obj-$(CONFIG_MFD_STW481X) += stw481x.o
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obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
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intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
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obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
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158
drivers/mfd/intel_soc_pmic_crc.c
Normal file
158
drivers/mfd/intel_soc_pmic_crc.c
Normal file
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@ -0,0 +1,158 @@
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/*
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* intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
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*
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* Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Author: Yang, Bin <bin.yang@intel.com>
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* Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
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*/
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#include <linux/mfd/core.h>
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#include <linux/interrupt.h>
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#include <linux/regmap.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include "intel_soc_pmic_core.h"
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#define CRYSTAL_COVE_MAX_REGISTER 0xC6
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#define CRYSTAL_COVE_REG_IRQLVL1 0x02
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#define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
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#define CRYSTAL_COVE_IRQ_PWRSRC 0
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#define CRYSTAL_COVE_IRQ_THRM 1
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#define CRYSTAL_COVE_IRQ_BCU 2
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#define CRYSTAL_COVE_IRQ_ADC 3
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#define CRYSTAL_COVE_IRQ_CHGR 4
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#define CRYSTAL_COVE_IRQ_GPIO 5
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#define CRYSTAL_COVE_IRQ_VHDMIOCP 6
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static struct resource gpio_resources[] = {
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{
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.name = "GPIO",
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.start = CRYSTAL_COVE_IRQ_GPIO,
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.end = CRYSTAL_COVE_IRQ_GPIO,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource pwrsrc_resources[] = {
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{
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.name = "PWRSRC",
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.start = CRYSTAL_COVE_IRQ_PWRSRC,
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.end = CRYSTAL_COVE_IRQ_PWRSRC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource adc_resources[] = {
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{
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.name = "ADC",
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.start = CRYSTAL_COVE_IRQ_ADC,
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.end = CRYSTAL_COVE_IRQ_ADC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource thermal_resources[] = {
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{
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.name = "THERMAL",
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.start = CRYSTAL_COVE_IRQ_THRM,
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.end = CRYSTAL_COVE_IRQ_THRM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource bcu_resources[] = {
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{
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.name = "BCU",
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.start = CRYSTAL_COVE_IRQ_BCU,
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.end = CRYSTAL_COVE_IRQ_BCU,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct mfd_cell crystal_cove_dev[] = {
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{
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.name = "crystal_cove_pwrsrc",
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.num_resources = ARRAY_SIZE(pwrsrc_resources),
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.resources = pwrsrc_resources,
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},
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{
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.name = "crystal_cove_adc",
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.num_resources = ARRAY_SIZE(adc_resources),
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.resources = adc_resources,
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},
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{
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.name = "crystal_cove_thermal",
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.num_resources = ARRAY_SIZE(thermal_resources),
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.resources = thermal_resources,
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},
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{
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.name = "crystal_cove_bcu",
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.num_resources = ARRAY_SIZE(bcu_resources),
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.resources = bcu_resources,
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},
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{
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.name = "crystal_cove_gpio",
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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},
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};
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static struct regmap_config crystal_cove_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = CRYSTAL_COVE_MAX_REGISTER,
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.cache_type = REGCACHE_NONE,
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};
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static const struct regmap_irq crystal_cove_irqs[] = {
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[CRYSTAL_COVE_IRQ_PWRSRC] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
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},
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[CRYSTAL_COVE_IRQ_THRM] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_THRM),
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},
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[CRYSTAL_COVE_IRQ_BCU] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_BCU),
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},
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[CRYSTAL_COVE_IRQ_ADC] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_ADC),
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},
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[CRYSTAL_COVE_IRQ_CHGR] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
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},
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[CRYSTAL_COVE_IRQ_GPIO] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
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},
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[CRYSTAL_COVE_IRQ_VHDMIOCP] = {
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.mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
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},
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};
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static struct regmap_irq_chip crystal_cove_irq_chip = {
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.name = "Crystal Cove",
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.irqs = crystal_cove_irqs,
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.num_irqs = ARRAY_SIZE(crystal_cove_irqs),
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.num_regs = 1,
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.status_base = CRYSTAL_COVE_REG_IRQLVL1,
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.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
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};
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struct intel_soc_pmic_config intel_soc_pmic_config_crc = {
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.irq_flags = IRQF_TRIGGER_RISING,
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.cell_dev = crystal_cove_dev,
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.n_cell_devs = ARRAY_SIZE(crystal_cove_dev),
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.regmap_config = &crystal_cove_regmap_config,
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.irq_chip = &crystal_cove_irq_chip,
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};
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