perf, x86: P4 PMU: Fix spurious NMI messages
Several people have reported spurious unknown NMI messages on some P4 CPUs. This patch fixes it by checking for an overflow (negative counter values) directly, instead of relying on the P4_CCCR_OVF bit. Reported-by: George Spelvin <linux@horizon.com> Reported-by: Meelis Roos <mroos@linux.ee> Reported-by: Don Zickus <dzickus@redhat.com> Reported-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Lin Ming <ming.m.lin@intel.com> Cc: Don Zickus <dzickus@redhat.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <AANLkTinfuTfCck_FfaOHrDqQZZehtRzkBum4SpFoO=KJ@mail.gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -22,6 +22,7 @@
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#define ARCH_P4_CNTRVAL_BITS (40)
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#define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
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#define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
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#define P4_ESCR_EVENT_MASK 0x7e000000U
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#define P4_ESCR_EVENT_SHIFT 25
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@ -770,9 +770,14 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
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return 1;
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}
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/* it might be unflagged overflow */
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rdmsrl(hwc->event_base + hwc->idx, v);
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if (!(v & ARCH_P4_CNTRVAL_MASK))
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/*
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* In some circumstances the overflow might issue an NMI but did
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* not set P4_CCCR_OVF bit. Because a counter holds a negative value
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* we simply check for high bit being set, if it's cleared it means
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* the counter has reached zero value and continued counting before
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* real NMI signal was received:
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*/
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if (!(v & ARCH_P4_UNFLAGGED_BIT))
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return 1;
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return 0;
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