radeon: use max_bus_speed to activate gen2 speeds
radeon currently uses a drm function to get the speed capabilities for the bus, drm_pcie_get_speed_cap_mask. However, this is a non-standard method of performing this detection and this patch changes it to use the max_bus_speed attribute. From: Lucas Kannebley Tavares <lucaskt@linux.vnet.ibm.com> Signed-off-by: Kleber Sacilotto de Souza <klebers@linux.vnet.ibm.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -4999,8 +4999,7 @@ void evergreen_fini(struct radeon_device *rdev)
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void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
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{
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u32 link_width_cntl, speed_cntl, mask;
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int ret;
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u32 link_width_cntl, speed_cntl;
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if (radeon_pcie_gen2 == 0)
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return;
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@ -5015,11 +5014,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
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if (ASIC_IS_X2(rdev))
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return;
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ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
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if (ret != 0)
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return;
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if (!(mask & DRM_PCIE_SPEED_50))
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if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
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(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
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return;
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speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
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@ -4631,8 +4631,6 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
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{
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u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
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u16 link_cntl2;
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u32 mask;
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int ret;
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if (radeon_pcie_gen2 == 0)
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return;
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@ -4651,11 +4649,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
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if (rdev->family <= CHIP_R600)
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return;
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ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
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if (ret != 0)
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return;
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if (!(mask & DRM_PCIE_SPEED_50))
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if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
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(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
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return;
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speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
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@ -2111,8 +2111,6 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
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{
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u32 link_width_cntl, lanes, speed_cntl, tmp;
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u16 link_cntl2;
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u32 mask;
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int ret;
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if (radeon_pcie_gen2 == 0)
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return;
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@ -2127,11 +2125,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
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if (ASIC_IS_X2(rdev))
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return;
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ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
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if (ret != 0)
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return;
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if (!(mask & DRM_PCIE_SPEED_50))
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if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
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(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
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return;
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DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
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