clocksource: sun4i: Fix bug when switching from periodic to oneshot modes
The interval was firing at was set up at probe time, and only changed in the set_next_event, and never changed back, which is not really what is expected. When enabling the periodic mode, now set an interval to tick every jiffy. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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@ -38,6 +38,7 @@
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#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
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#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
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static void __iomem *timer_base;
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static void __iomem *timer_base;
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static u32 ticks_per_jiffy;
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/*
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/*
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* When we disable a timer, we need to wait at least for 2 cycles of
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* When we disable a timer, we need to wait at least for 2 cycles of
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@ -74,7 +75,8 @@ static void sun4i_clkevt_time_start(u8 timer, bool periodic)
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else
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else
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val |= TIMER_CTL_ONESHOT;
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val |= TIMER_CTL_ONESHOT;
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writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
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writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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timer_base + TIMER_CTL_REG(timer));
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}
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}
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static void sun4i_clkevt_mode(enum clock_event_mode mode,
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static void sun4i_clkevt_mode(enum clock_event_mode mode,
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@ -83,6 +85,7 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode,
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switch (mode) {
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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case CLOCK_EVT_MODE_PERIODIC:
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sun4i_clkevt_time_stop(0);
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sun4i_clkevt_time_stop(0);
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sun4i_clkevt_time_setup(0, ticks_per_jiffy);
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sun4i_clkevt_time_start(0, true);
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sun4i_clkevt_time_start(0, true);
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break;
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_ONESHOT:
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@ -169,9 +172,9 @@ static void __init sun4i_timer_init(struct device_node *node)
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clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
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clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
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rate, 300, 32, clocksource_mmio_readl_down);
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rate, 300, 32, clocksource_mmio_readl_down);
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writel(rate / HZ, timer_base + TIMER_INTVAL_REG(0));
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ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M) | TIMER_CTL_RELOAD,
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writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
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timer_base + TIMER_CTL_REG(0));
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timer_base + TIMER_CTL_REG(0));
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ret = setup_irq(irq, &sun4i_timer_irq);
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ret = setup_irq(irq, &sun4i_timer_irq);
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