soc/tegra: fuse: Unify Tegra20 and Tegra30 drivers
Unifying the drivers makes it easier to restrict the legacy probing paths to 32-bit ARM. This in turn will come in handy as support for new 64-bit ARM SoCs is added. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
297c4f3dcb
commit
7e939de1b2
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@ -82,9 +82,6 @@
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#define TEGRA_EMC_BASE 0x7000F400
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#define TEGRA_EMC_SIZE SZ_1K
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#define TEGRA_FUSE_BASE 0x7000F800
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#define TEGRA_FUSE_SIZE SZ_1K
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#define TEGRA_EMC0_BASE 0x7001A000
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#define TEGRA_EMC0_SIZE SZ_2K
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@ -6,3 +6,4 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += speedo-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += speedo-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += speedo-tegra114.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += speedo-tegra124.o
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obj-$(CONFIG_ARCH_TEGRA_132_SOC) += speedo-tegra124.o
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@ -15,9 +15,10 @@
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*
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/kobject.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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@ -28,8 +29,6 @@
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#include "fuse.h"
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static u32 (*fuse_readl)(const unsigned int offset);
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static int fuse_size;
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struct tegra_sku_info tegra_sku_info;
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EXPORT_SYMBOL(tegra_sku_info);
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@ -42,11 +41,11 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
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[TEGRA_REVISION_A04] = "A04",
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};
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static u8 fuse_readb(const unsigned int offset)
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static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset)
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{
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u32 val;
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val = fuse_readl(round_down(offset, 4));
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val = fuse->read(fuse, round_down(offset, 4));
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val >>= (offset % 4) * 8;
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val &= 0xff;
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@ -54,19 +53,21 @@ static u8 fuse_readb(const unsigned int offset)
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}
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static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t pos, size_t size)
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struct bin_attribute *attr, char *buf,
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loff_t pos, size_t size)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct tegra_fuse *fuse = dev_get_drvdata(dev);
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int i;
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if (pos < 0 || pos >= fuse_size)
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if (pos < 0 || pos >= attr->size)
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return 0;
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if (size > fuse_size - pos)
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size = fuse_size - pos;
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if (size > attr->size - pos)
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size = attr->size - pos;
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for (i = 0; i < size; i++)
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buf[i] = fuse_readb(pos + i);
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buf[i] = fuse_readb(fuse, pos + i);
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return i;
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}
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@ -76,6 +77,14 @@ static struct bin_attribute fuse_bin_attr = {
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.read = fuse_read,
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};
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static int tegra_fuse_create_sysfs(struct device *dev, unsigned int size,
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const struct tegra_fuse_info *info)
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{
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fuse_bin_attr.size = size;
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return device_create_bin_file(dev, &fuse_bin_attr);
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}
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static const struct of_device_id car_match[] __initconst = {
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{ .compatible = "nvidia,tegra20-car", },
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{ .compatible = "nvidia,tegra30-car", },
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@ -85,6 +94,101 @@ static const struct of_device_id car_match[] __initconst = {
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{},
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};
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static struct tegra_fuse *fuse = &(struct tegra_fuse) {
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.base = NULL,
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.soc = NULL,
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};
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static const struct of_device_id tegra_fuse_match[] = {
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#ifdef CONFIG_ARCH_TEGRA_132_SOC
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{ .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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{ .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
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#endif
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{ /* sentinel */ }
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};
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static int tegra_fuse_probe(struct platform_device *pdev)
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{
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void __iomem *base = fuse->base;
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struct resource *res;
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int err;
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/* take over the memory region from the early initialization */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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fuse->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(fuse->base))
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return PTR_ERR(fuse->base);
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fuse->clk = devm_clk_get(&pdev->dev, "fuse");
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if (IS_ERR(fuse->clk)) {
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dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
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PTR_ERR(fuse->clk));
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return PTR_ERR(fuse->clk);
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}
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platform_set_drvdata(pdev, fuse);
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fuse->dev = &pdev->dev;
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if (fuse->soc->probe) {
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err = fuse->soc->probe(fuse);
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if (err < 0)
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return err;
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}
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if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size,
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fuse->soc->info))
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return -ENODEV;
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/* release the early I/O memory mapping */
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iounmap(base);
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return 0;
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}
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static struct platform_driver tegra_fuse_driver = {
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.driver = {
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.name = "tegra-fuse",
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.of_match_table = tegra_fuse_match,
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.suppress_bind_attrs = true,
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},
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.probe = tegra_fuse_probe,
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};
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module_platform_driver(tegra_fuse_driver);
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bool __init tegra_fuse_read_spare(unsigned int spare)
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{
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unsigned int offset = fuse->soc->info->spare + spare * 4;
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return fuse->read_early(fuse, offset) & 1;
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}
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u32 __init tegra_fuse_read_early(unsigned int offset)
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{
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return fuse->read_early(fuse, offset);
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}
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int tegra_fuse_readl(unsigned long offset, u32 *value)
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{
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if (!fuse->read)
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return -EPROBE_DEFER;
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*value = fuse->read(fuse, offset);
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return 0;
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}
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EXPORT_SYMBOL(tegra_fuse_readl);
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static void tegra_enable_fuse_clk(void __iomem *base)
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{
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u32 reg;
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@ -102,56 +206,99 @@ static void tegra_enable_fuse_clk(void __iomem *base)
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writel(reg, base + 0x14);
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}
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int tegra_fuse_readl(unsigned long offset, u32 *value)
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{
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if (!fuse_readl)
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return -EPROBE_DEFER;
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*value = fuse_readl(offset);
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return 0;
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}
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EXPORT_SYMBOL(tegra_fuse_readl);
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int tegra_fuse_create_sysfs(struct device *dev, int size,
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u32 (*readl)(const unsigned int offset))
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{
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if (fuse_size)
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return -ENODEV;
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fuse_bin_attr.size = size;
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fuse_bin_attr.read = fuse_read;
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fuse_size = size;
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fuse_readl = readl;
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return device_create_bin_file(dev, &fuse_bin_attr);
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}
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static int __init tegra_init_fuse(void)
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{
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const struct of_device_id *match;
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struct device_node *np;
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void __iomem *car_base;
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if (!soc_is_tegra())
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return 0;
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struct resource regs;
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tegra_init_apbmisc();
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np = of_find_matching_node(NULL, car_match);
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car_base = of_iomap(np, 0);
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if (car_base) {
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tegra_enable_fuse_clk(car_base);
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iounmap(car_base);
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np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
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if (!np) {
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/*
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* Fall back to legacy initialization for 32-bit ARM only. All
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* 64-bit ARM device tree files for Tegra are required to have
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* a FUSE node.
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*
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* This is for backwards-compatibility with old device trees
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* that didn't contain a FUSE node.
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*/
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if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
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u8 chip = tegra_get_chip_id();
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regs.start = 0x7000f800;
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regs.end = 0x7000fbff;
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regs.flags = IORESOURCE_MEM;
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switch (chip) {
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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case TEGRA20:
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fuse->soc = &tegra20_fuse_soc;
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break;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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case TEGRA30:
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fuse->soc = &tegra30_fuse_soc;
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break;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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case TEGRA114:
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fuse->soc = &tegra114_fuse_soc;
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break;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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case TEGRA124:
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fuse->soc = &tegra124_fuse_soc;
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break;
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#endif
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default:
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pr_warn("Unsupported SoC: %02x\n", chip);
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break;
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}
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} else {
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/*
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* At this point we're not running on Tegra, so play
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* nice with multi-platform kernels.
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*/
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return 0;
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}
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} else {
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pr_err("Could not enable fuse clk. ioremap tegra car failed.\n");
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/*
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* Extract information from the device tree if we've found a
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* matching node.
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*/
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if (of_address_to_resource(np, 0, ®s) < 0) {
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pr_err("failed to get FUSE register\n");
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return -ENXIO;
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}
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fuse->soc = match->data;
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}
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np = of_find_matching_node(NULL, car_match);
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if (np) {
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void __iomem *base = of_iomap(np, 0);
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if (base) {
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tegra_enable_fuse_clk(base);
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iounmap(base);
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} else {
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pr_err("failed to map clock registers\n");
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return -ENXIO;
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}
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}
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fuse->base = ioremap_nocache(regs.start, resource_size(®s));
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if (!fuse->base) {
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pr_err("failed to map FUSE registers\n");
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return -ENXIO;
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}
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if (tegra_get_chip_id() == TEGRA20)
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tegra20_init_fuse_early();
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else
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tegra30_init_fuse_early();
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fuse->soc->init(fuse);
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pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
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tegra_revision_name[tegra_sku_info.revision],
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@ -34,159 +34,107 @@
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#include "fuse.h"
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#define FUSE_BEGIN 0x100
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#define FUSE_SIZE 0x1f8
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#define FUSE_UID_LOW 0x08
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#define FUSE_UID_HIGH 0x0c
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static phys_addr_t fuse_phys;
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static struct clk *fuse_clk;
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static void __iomem __initdata *fuse_base;
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static DEFINE_MUTEX(apb_dma_lock);
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static DECLARE_COMPLETION(apb_dma_wait);
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static struct dma_chan *apb_dma_chan;
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static struct dma_slave_config dma_sconfig;
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static u32 *apb_buffer;
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static dma_addr_t apb_buffer_phys;
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static u32 tegra20_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
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{
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return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
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}
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static void apb_dma_complete(void *args)
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{
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complete(&apb_dma_wait);
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struct tegra_fuse *fuse = args;
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complete(&fuse->apbdma.wait);
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}
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static u32 tegra20_fuse_readl(const unsigned int offset)
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static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
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{
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int ret;
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u32 val = 0;
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unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
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struct dma_async_tx_descriptor *dma_desc;
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unsigned long time_left;
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u32 value = 0;
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int err;
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mutex_lock(&apb_dma_lock);
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mutex_lock(&fuse->apbdma.lock);
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dma_sconfig.src_addr = fuse_phys + FUSE_BEGIN + offset;
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ret = dmaengine_slave_config(apb_dma_chan, &dma_sconfig);
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if (ret)
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fuse->apbdma.config.src_addr = fuse->apbdma.phys + FUSE_BEGIN + offset;
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err = dmaengine_slave_config(fuse->apbdma.chan, &fuse->apbdma.config);
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if (err)
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goto out;
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dma_desc = dmaengine_prep_slave_single(apb_dma_chan, apb_buffer_phys,
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sizeof(u32), DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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dma_desc = dmaengine_prep_slave_single(fuse->apbdma.chan,
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fuse->apbdma.phys,
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sizeof(u32), DMA_DEV_TO_MEM,
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flags);
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if (!dma_desc)
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goto out;
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dma_desc->callback = apb_dma_complete;
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dma_desc->callback_param = NULL;
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dma_desc->callback_param = fuse;
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reinit_completion(&apb_dma_wait);
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reinit_completion(&fuse->apbdma.wait);
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clk_prepare_enable(fuse_clk);
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clk_prepare_enable(fuse->clk);
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dmaengine_submit(dma_desc);
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dma_async_issue_pending(apb_dma_chan);
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time_left = wait_for_completion_timeout(&apb_dma_wait,
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dma_async_issue_pending(fuse->apbdma.chan);
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time_left = wait_for_completion_timeout(&fuse->apbdma.wait,
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msecs_to_jiffies(50));
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if (WARN(time_left == 0, "apb read dma timed out"))
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dmaengine_terminate_all(apb_dma_chan);
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dmaengine_terminate_all(fuse->apbdma.chan);
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else
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val = *apb_buffer;
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value = *fuse->apbdma.virt;
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clk_disable_unprepare(fuse->clk);
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clk_disable_unprepare(fuse_clk);
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out:
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mutex_unlock(&apb_dma_lock);
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return val;
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mutex_unlock(&fuse->apbdma.lock);
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return value;
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}
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static const struct of_device_id tegra20_fuse_of_match[] = {
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{ .compatible = "nvidia,tegra20-efuse" },
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{},
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};
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static int apb_dma_init(void)
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static int tegra20_fuse_probe(struct tegra_fuse *fuse)
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{
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dma_cap_mask_t mask;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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apb_dma_chan = dma_request_channel(mask, NULL, NULL);
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if (!apb_dma_chan)
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fuse->apbdma.chan = dma_request_channel(mask, NULL, NULL);
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if (!fuse->apbdma.chan)
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return -EPROBE_DEFER;
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apb_buffer = dma_alloc_coherent(NULL, sizeof(u32), &apb_buffer_phys,
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GFP_KERNEL);
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if (!apb_buffer) {
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dma_release_channel(apb_dma_chan);
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fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32),
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&fuse->apbdma.phys,
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GFP_KERNEL);
|
||||
if (!fuse->apbdma.virt) {
|
||||
dma_release_channel(fuse->apbdma.chan);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
dma_sconfig.src_maxburst = 1;
|
||||
dma_sconfig.dst_maxburst = 1;
|
||||
fuse->apbdma.config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
fuse->apbdma.config.src_maxburst = 1;
|
||||
fuse->apbdma.config.dst_maxburst = 1;
|
||||
|
||||
init_completion(&fuse->apbdma.wait);
|
||||
mutex_init(&fuse->apbdma.lock);
|
||||
fuse->read = tegra20_fuse_read;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra20_fuse_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
int err;
|
||||
|
||||
fuse_clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(fuse_clk)) {
|
||||
dev_err(&pdev->dev, "missing clock");
|
||||
return PTR_ERR(fuse_clk);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -EINVAL;
|
||||
fuse_phys = res->start;
|
||||
|
||||
err = apb_dma_init();
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (tegra_fuse_create_sysfs(&pdev->dev, FUSE_SIZE, tegra20_fuse_readl))
|
||||
return -ENODEV;
|
||||
|
||||
dev_dbg(&pdev->dev, "loaded\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra20_fuse_driver = {
|
||||
.probe = tegra20_fuse_probe,
|
||||
.driver = {
|
||||
.name = "tegra20_fuse",
|
||||
.of_match_table = tegra20_fuse_of_match,
|
||||
}
|
||||
static const struct tegra_fuse_info tegra20_fuse_info = {
|
||||
.read = tegra20_fuse_read,
|
||||
.size = 0x1f8,
|
||||
.spare = 0x100,
|
||||
};
|
||||
|
||||
static int __init tegra20_fuse_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra20_fuse_driver);
|
||||
}
|
||||
postcore_initcall(tegra20_fuse_init);
|
||||
|
||||
/* Early boot code. This code is called before the devices are created */
|
||||
|
||||
u32 __init tegra20_fuse_early(const unsigned int offset)
|
||||
{
|
||||
return readl_relaxed(fuse_base + FUSE_BEGIN + offset);
|
||||
}
|
||||
|
||||
bool __init tegra20_spare_fuse_early(int spare_bit)
|
||||
{
|
||||
u32 offset = spare_bit * 4;
|
||||
bool value;
|
||||
|
||||
value = tegra20_fuse_early(offset + 0x100);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static void __init tegra20_fuse_add_randomness(void)
|
||||
{
|
||||
u32 randomness[7];
|
||||
|
|
@ -198,19 +146,24 @@ static void __init tegra20_fuse_add_randomness(void)
|
|||
randomness[3] |= tegra_sku_info.core_process_id;
|
||||
randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
|
||||
randomness[4] |= tegra_sku_info.soc_speedo_id;
|
||||
randomness[5] = tegra20_fuse_early(FUSE_UID_LOW);
|
||||
randomness[6] = tegra20_fuse_early(FUSE_UID_HIGH);
|
||||
randomness[5] = tegra_fuse_read_early(FUSE_UID_LOW);
|
||||
randomness[6] = tegra_fuse_read_early(FUSE_UID_HIGH);
|
||||
|
||||
add_device_randomness(randomness, sizeof(randomness));
|
||||
}
|
||||
|
||||
void __init tegra20_init_fuse_early(void)
|
||||
static void __init tegra20_fuse_init(struct tegra_fuse *fuse)
|
||||
{
|
||||
fuse_base = ioremap(TEGRA_FUSE_BASE, TEGRA_FUSE_SIZE);
|
||||
fuse->read_early = tegra20_fuse_read_early;
|
||||
|
||||
tegra_init_revision();
|
||||
tegra20_init_speedo_data(&tegra_sku_info);
|
||||
fuse->soc->speedo_init(&tegra_sku_info);
|
||||
tegra20_fuse_add_randomness();
|
||||
|
||||
iounmap(fuse_base);
|
||||
}
|
||||
|
||||
const struct tegra_fuse_soc tegra20_fuse_soc = {
|
||||
.init = tegra20_fuse_init,
|
||||
.speedo_init = tegra20_init_speedo_data,
|
||||
.probe = tegra20_fuse_probe,
|
||||
.info = &tegra20_fuse_info,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -42,114 +42,33 @@
|
|||
|
||||
#define FUSE_HAS_REVISION_INFO BIT(0)
|
||||
|
||||
enum speedo_idx {
|
||||
SPEEDO_TEGRA30 = 0,
|
||||
SPEEDO_TEGRA114,
|
||||
SPEEDO_TEGRA124,
|
||||
};
|
||||
|
||||
struct tegra_fuse_info {
|
||||
int size;
|
||||
int spare_bit;
|
||||
enum speedo_idx speedo_idx;
|
||||
};
|
||||
|
||||
static void __iomem *fuse_base;
|
||||
static struct clk *fuse_clk;
|
||||
static const struct tegra_fuse_info *fuse_info;
|
||||
|
||||
u32 tegra30_fuse_readl(const unsigned int offset)
|
||||
#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_114_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_124_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_132_SOC)
|
||||
static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* early in the boot, the fuse clock will be enabled by
|
||||
* tegra_init_fuse()
|
||||
*/
|
||||
|
||||
if (fuse_clk)
|
||||
clk_prepare_enable(fuse_clk);
|
||||
|
||||
val = readl_relaxed(fuse_base + FUSE_BEGIN + offset);
|
||||
|
||||
if (fuse_clk)
|
||||
clk_disable_unprepare(fuse_clk);
|
||||
|
||||
return val;
|
||||
return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
|
||||
}
|
||||
|
||||
static const struct tegra_fuse_info tegra30_info = {
|
||||
.size = 0x2a4,
|
||||
.spare_bit = 0x144,
|
||||
.speedo_idx = SPEEDO_TEGRA30,
|
||||
};
|
||||
|
||||
static const struct tegra_fuse_info tegra114_info = {
|
||||
.size = 0x2a0,
|
||||
.speedo_idx = SPEEDO_TEGRA114,
|
||||
};
|
||||
|
||||
static const struct tegra_fuse_info tegra124_info = {
|
||||
.size = 0x300,
|
||||
.speedo_idx = SPEEDO_TEGRA124,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra30_fuse_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_info },
|
||||
{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_info },
|
||||
{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_info },
|
||||
{},
|
||||
};
|
||||
|
||||
static int tegra30_fuse_probe(struct platform_device *pdev)
|
||||
static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
|
||||
{
|
||||
const struct of_device_id *of_dev_id;
|
||||
u32 value;
|
||||
int err;
|
||||
|
||||
of_dev_id = of_match_device(tegra30_fuse_of_match, &pdev->dev);
|
||||
if (!of_dev_id)
|
||||
return -ENODEV;
|
||||
|
||||
fuse_clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(fuse_clk)) {
|
||||
dev_err(&pdev->dev, "missing clock");
|
||||
return PTR_ERR(fuse_clk);
|
||||
err = clk_prepare_enable(fuse->clk);
|
||||
if (err < 0) {
|
||||
dev_err(fuse->dev, "failed to enable FUSE clock: %d\n", err);
|
||||
return 0;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
value = readl_relaxed(fuse->base + FUSE_BEGIN + offset);
|
||||
|
||||
if (tegra_fuse_create_sysfs(&pdev->dev, fuse_info->size,
|
||||
tegra30_fuse_readl))
|
||||
return -ENODEV;
|
||||
clk_disable_unprepare(fuse->clk);
|
||||
|
||||
dev_dbg(&pdev->dev, "loaded\n");
|
||||
|
||||
return 0;
|
||||
return value;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra30_fuse_driver = {
|
||||
.probe = tegra30_fuse_probe,
|
||||
.driver = {
|
||||
.name = "tegra_fuse",
|
||||
.of_match_table = tegra30_fuse_of_match,
|
||||
}
|
||||
};
|
||||
|
||||
static int __init tegra30_fuse_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra30_fuse_driver);
|
||||
}
|
||||
postcore_initcall(tegra30_fuse_init);
|
||||
|
||||
/* Early boot code. This code is called before the devices are created */
|
||||
|
||||
typedef void (*speedo_f)(struct tegra_sku_info *sku_info);
|
||||
|
||||
static speedo_f __initdata speedo_tbl[] = {
|
||||
[SPEEDO_TEGRA30] = tegra30_init_speedo_data,
|
||||
[SPEEDO_TEGRA114] = tegra114_init_speedo_data,
|
||||
[SPEEDO_TEGRA124] = tegra124_init_speedo_data,
|
||||
};
|
||||
|
||||
static void __init tegra30_fuse_add_randomness(void)
|
||||
{
|
||||
u32 randomness[12];
|
||||
|
|
@ -161,64 +80,64 @@ static void __init tegra30_fuse_add_randomness(void)
|
|||
randomness[3] |= tegra_sku_info.core_process_id;
|
||||
randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
|
||||
randomness[4] |= tegra_sku_info.soc_speedo_id;
|
||||
randomness[5] = tegra30_fuse_readl(FUSE_VENDOR_CODE);
|
||||
randomness[6] = tegra30_fuse_readl(FUSE_FAB_CODE);
|
||||
randomness[7] = tegra30_fuse_readl(FUSE_LOT_CODE_0);
|
||||
randomness[8] = tegra30_fuse_readl(FUSE_LOT_CODE_1);
|
||||
randomness[9] = tegra30_fuse_readl(FUSE_WAFER_ID);
|
||||
randomness[10] = tegra30_fuse_readl(FUSE_X_COORDINATE);
|
||||
randomness[11] = tegra30_fuse_readl(FUSE_Y_COORDINATE);
|
||||
randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);
|
||||
randomness[6] = tegra_fuse_read_early(FUSE_FAB_CODE);
|
||||
randomness[7] = tegra_fuse_read_early(FUSE_LOT_CODE_0);
|
||||
randomness[8] = tegra_fuse_read_early(FUSE_LOT_CODE_1);
|
||||
randomness[9] = tegra_fuse_read_early(FUSE_WAFER_ID);
|
||||
randomness[10] = tegra_fuse_read_early(FUSE_X_COORDINATE);
|
||||
randomness[11] = tegra_fuse_read_early(FUSE_Y_COORDINATE);
|
||||
|
||||
add_device_randomness(randomness, sizeof(randomness));
|
||||
}
|
||||
|
||||
static void __init legacy_fuse_init(void)
|
||||
static void __init tegra30_fuse_init(struct tegra_fuse *fuse)
|
||||
{
|
||||
switch (tegra_get_chip_id()) {
|
||||
case TEGRA30:
|
||||
fuse_info = &tegra30_info;
|
||||
break;
|
||||
case TEGRA114:
|
||||
fuse_info = &tegra114_info;
|
||||
break;
|
||||
case TEGRA124:
|
||||
case TEGRA132:
|
||||
fuse_info = &tegra124_info;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
fuse_base = ioremap(TEGRA_FUSE_BASE, TEGRA_FUSE_SIZE);
|
||||
}
|
||||
|
||||
bool __init tegra30_spare_fuse(int spare_bit)
|
||||
{
|
||||
u32 offset = fuse_info->spare_bit + spare_bit * 4;
|
||||
|
||||
return tegra30_fuse_readl(offset) & 1;
|
||||
}
|
||||
|
||||
void __init tegra30_init_fuse_early(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
const struct of_device_id *of_match;
|
||||
|
||||
np = of_find_matching_node_and_match(NULL, tegra30_fuse_of_match,
|
||||
&of_match);
|
||||
if (np) {
|
||||
fuse_base = of_iomap(np, 0);
|
||||
fuse_info = (struct tegra_fuse_info *)of_match->data;
|
||||
} else
|
||||
legacy_fuse_init();
|
||||
|
||||
if (!fuse_base) {
|
||||
pr_warn("fuse DT node missing and unknown chip id: 0x%02x\n",
|
||||
tegra_get_chip_id());
|
||||
return;
|
||||
}
|
||||
fuse->read_early = tegra30_fuse_read_early;
|
||||
fuse->read = tegra30_fuse_read;
|
||||
|
||||
tegra_init_revision();
|
||||
speedo_tbl[fuse_info->speedo_idx](&tegra_sku_info);
|
||||
fuse->soc->speedo_init(&tegra_sku_info);
|
||||
tegra30_fuse_add_randomness();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
static const struct tegra_fuse_info tegra30_fuse_info = {
|
||||
.read = tegra30_fuse_read,
|
||||
.size = 0x2a4,
|
||||
.spare = 0x144,
|
||||
};
|
||||
|
||||
const struct tegra_fuse_soc tegra30_fuse_soc = {
|
||||
.init = tegra30_fuse_init,
|
||||
.speedo_init = tegra30_init_speedo_data,
|
||||
.info = &tegra30_fuse_info,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
static const struct tegra_fuse_info tegra114_fuse_info = {
|
||||
.read = tegra30_fuse_read,
|
||||
.size = 0x2a0,
|
||||
};
|
||||
|
||||
const struct tegra_fuse_soc tegra114_fuse_soc = {
|
||||
.init = tegra30_fuse_init,
|
||||
.speedo_init = tegra114_init_speedo_data,
|
||||
.info = &tegra114_fuse_info,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
|
||||
static const struct tegra_fuse_info tegra124_fuse_info = {
|
||||
.read = tegra30_fuse_read,
|
||||
.size = 0x300,
|
||||
};
|
||||
|
||||
const struct tegra_fuse_soc tegra124_fuse_soc = {
|
||||
.init = tegra30_fuse_init,
|
||||
.speedo_init = tegra124_init_speedo_data,
|
||||
.info = &tegra124_fuse_info,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -19,53 +19,82 @@
|
|||
#ifndef __DRIVERS_MISC_TEGRA_FUSE_H
|
||||
#define __DRIVERS_MISC_TEGRA_FUSE_H
|
||||
|
||||
#define TEGRA_FUSE_BASE 0x7000f800
|
||||
#define TEGRA_FUSE_SIZE 0x400
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
int tegra_fuse_create_sysfs(struct device *dev, int size,
|
||||
u32 (*readl)(const unsigned int offset));
|
||||
struct tegra_fuse;
|
||||
|
||||
struct tegra_fuse_info {
|
||||
u32 (*read)(struct tegra_fuse *fuse, unsigned int offset);
|
||||
unsigned int size;
|
||||
unsigned int spare;
|
||||
};
|
||||
|
||||
struct tegra_fuse_soc {
|
||||
void (*init)(struct tegra_fuse *fuse);
|
||||
void (*speedo_init)(struct tegra_sku_info *info);
|
||||
int (*probe)(struct tegra_fuse *fuse);
|
||||
|
||||
const struct tegra_fuse_info *info;
|
||||
};
|
||||
|
||||
struct tegra_fuse {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
phys_addr_t phys;
|
||||
struct clk *clk;
|
||||
|
||||
u32 (*read_early)(struct tegra_fuse *fuse, unsigned int offset);
|
||||
u32 (*read)(struct tegra_fuse *fuse, unsigned int offset);
|
||||
const struct tegra_fuse_soc *soc;
|
||||
|
||||
/* APBDMA on Tegra20 */
|
||||
struct {
|
||||
struct mutex lock;
|
||||
struct completion wait;
|
||||
struct dma_chan *chan;
|
||||
struct dma_slave_config config;
|
||||
dma_addr_t phys;
|
||||
u32 *virt;
|
||||
} apbdma;
|
||||
};
|
||||
|
||||
bool tegra30_spare_fuse(int bit);
|
||||
u32 tegra30_fuse_readl(const unsigned int offset);
|
||||
void tegra30_init_fuse_early(void);
|
||||
void tegra_init_revision(void);
|
||||
void tegra_init_apbmisc(void);
|
||||
|
||||
bool __init tegra_fuse_read_spare(unsigned int spare);
|
||||
u32 __init tegra_fuse_read_early(unsigned int offset);
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
void tegra20_init_speedo_data(struct tegra_sku_info *sku_info);
|
||||
bool tegra20_spare_fuse_early(int spare_bit);
|
||||
void tegra20_init_fuse_early(void);
|
||||
u32 tegra20_fuse_early(const unsigned int offset);
|
||||
#else
|
||||
static inline void tegra20_init_speedo_data(struct tegra_sku_info *sku_info) {}
|
||||
static inline bool tegra20_spare_fuse_early(int spare_bit)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
static inline void tegra20_init_fuse_early(void) {}
|
||||
static inline u32 tegra20_fuse_early(const unsigned int offset)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
void tegra30_init_speedo_data(struct tegra_sku_info *sku_info);
|
||||
#else
|
||||
static inline void tegra30_init_speedo_data(struct tegra_sku_info *sku_info) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
void tegra114_init_speedo_data(struct tegra_sku_info *sku_info);
|
||||
#else
|
||||
static inline void tegra114_init_speedo_data(struct tegra_sku_info *sku_info) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_124_SOC
|
||||
#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
|
||||
void tegra124_init_speedo_data(struct tegra_sku_info *sku_info);
|
||||
#else
|
||||
static inline void tegra124_init_speedo_data(struct tegra_sku_info *sku_info) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
extern const struct tegra_fuse_soc tegra20_fuse_soc;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
extern const struct tegra_fuse_soc tegra30_fuse_soc;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
extern const struct tegra_fuse_soc tegra114_fuse_soc;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
|
||||
extern const struct tegra_fuse_soc tegra124_fuse_soc;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -74,8 +74,8 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
|
|||
}
|
||||
|
||||
if (rev == TEGRA_REVISION_A01) {
|
||||
tmp = tegra30_fuse_readl(0x270) << 1;
|
||||
tmp |= tegra30_fuse_readl(0x26c);
|
||||
tmp = tegra_fuse_read_early(0x270) << 1;
|
||||
tmp |= tegra_fuse_read_early(0x26c);
|
||||
if (!tmp)
|
||||
sku_info->cpu_speedo_id = 0;
|
||||
}
|
||||
|
|
@ -95,8 +95,8 @@ void __init tegra114_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
|
||||
rev_sku_to_speedo_ids(sku_info, &threshold);
|
||||
|
||||
cpu_speedo_val = tegra30_fuse_readl(0x12c) + 1024;
|
||||
core_speedo_val = tegra30_fuse_readl(0x134);
|
||||
cpu_speedo_val = tegra_fuse_read_early(0x12c) + 1024;
|
||||
core_speedo_val = tegra_fuse_read_early(0x134);
|
||||
|
||||
for (i = 0; i < CPU_PROCESS_CORNERS; i++)
|
||||
if (cpu_speedo_val < cpu_process_speedos[threshold][i])
|
||||
|
|
|
|||
|
|
@ -122,16 +122,16 @@ void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
|
||||
cpu_speedo_0_value = tegra30_fuse_readl(FUSE_CPU_SPEEDO_0);
|
||||
cpu_speedo_0_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
|
||||
|
||||
/* GPU Speedo is stored in CPU_SPEEDO_2 */
|
||||
sku_info->gpu_speedo_value = tegra30_fuse_readl(FUSE_CPU_SPEEDO_2);
|
||||
sku_info->gpu_speedo_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
|
||||
|
||||
soc_speedo_0_value = tegra30_fuse_readl(FUSE_SOC_SPEEDO_0);
|
||||
soc_speedo_0_value = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
|
||||
|
||||
cpu_iddq_value = tegra30_fuse_readl(FUSE_CPU_IDDQ);
|
||||
soc_iddq_value = tegra30_fuse_readl(FUSE_SOC_IDDQ);
|
||||
gpu_iddq_value = tegra30_fuse_readl(FUSE_GPU_IDDQ);
|
||||
cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
|
||||
soc_iddq_value = tegra_fuse_read_early(FUSE_SOC_IDDQ);
|
||||
gpu_iddq_value = tegra_fuse_read_early(FUSE_GPU_IDDQ);
|
||||
|
||||
sku_info->cpu_speedo_value = cpu_speedo_0_value;
|
||||
|
||||
|
|
@ -143,7 +143,7 @@ void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
|
||||
rev_sku_to_speedo_ids(sku_info, &threshold);
|
||||
|
||||
sku_info->cpu_iddq_value = tegra30_fuse_readl(FUSE_CPU_IDDQ);
|
||||
sku_info->cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
|
||||
|
||||
for (i = 0; i < GPU_PROCESS_CORNERS; i++)
|
||||
if (sku_info->gpu_speedo_value <
|
||||
|
|
|
|||
|
|
@ -80,8 +80,8 @@ void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
|
||||
val = 0;
|
||||
for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
|
||||
reg = tegra20_spare_fuse_early(i) |
|
||||
tegra20_spare_fuse_early(i + CPU_SPEEDO_REDUND_OFFS);
|
||||
reg = tegra_fuse_read_spare(i) |
|
||||
tegra_fuse_read_spare(i + CPU_SPEEDO_REDUND_OFFS);
|
||||
val = (val << 1) | (reg & 0x1);
|
||||
}
|
||||
val = val * SPEEDO_MULT;
|
||||
|
|
@ -95,8 +95,8 @@ void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
|
||||
val = 0;
|
||||
for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
|
||||
reg = tegra20_spare_fuse_early(i) |
|
||||
tegra20_spare_fuse_early(i + CORE_SPEEDO_REDUND_OFFS);
|
||||
reg = tegra_fuse_read_spare(i) |
|
||||
tegra_fuse_read_spare(i + CORE_SPEEDO_REDUND_OFFS);
|
||||
val = (val << 1) | (reg & 0x1);
|
||||
}
|
||||
val = val * SPEEDO_MULT;
|
||||
|
|
|
|||
|
|
@ -93,25 +93,25 @@ static void __init fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
|
|||
int bit_minus1;
|
||||
int bit_minus2;
|
||||
|
||||
reg = tegra30_fuse_readl(FUSE_SPEEDO_CALIB_0);
|
||||
reg = tegra_fuse_read_early(FUSE_SPEEDO_CALIB_0);
|
||||
|
||||
*speedo_lp = (reg & 0xFFFF) * 4;
|
||||
*speedo_g = ((reg >> 16) & 0xFFFF) * 4;
|
||||
|
||||
ate_ver = tegra30_fuse_readl(FUSE_TEST_PROG_VER);
|
||||
ate_ver = tegra_fuse_read_early(FUSE_TEST_PROG_VER);
|
||||
pr_debug("Tegra ATE prog ver %d.%d\n", ate_ver/10, ate_ver%10);
|
||||
|
||||
if (ate_ver >= 26) {
|
||||
bit_minus1 = tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS1);
|
||||
bit_minus1 |= tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
|
||||
bit_minus2 = tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS2);
|
||||
bit_minus2 |= tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
|
||||
bit_minus1 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1);
|
||||
bit_minus1 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1_R);
|
||||
bit_minus2 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2);
|
||||
bit_minus2 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2_R);
|
||||
*speedo_lp |= (bit_minus1 << 1) | bit_minus2;
|
||||
|
||||
bit_minus1 = tegra30_spare_fuse(G_SPEEDO_BIT_MINUS1);
|
||||
bit_minus1 |= tegra30_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
|
||||
bit_minus2 = tegra30_spare_fuse(G_SPEEDO_BIT_MINUS2);
|
||||
bit_minus2 |= tegra30_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
|
||||
bit_minus1 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1);
|
||||
bit_minus1 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1_R);
|
||||
bit_minus2 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2);
|
||||
bit_minus2 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2_R);
|
||||
*speedo_g |= (bit_minus1 << 1) | bit_minus2;
|
||||
} else {
|
||||
*speedo_lp |= 0x3;
|
||||
|
|
@ -121,7 +121,7 @@ static void __init fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
|
|||
|
||||
static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info)
|
||||
{
|
||||
int package_id = tegra30_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
|
||||
int package_id = tegra_fuse_read_early(FUSE_PACKAGE_INFO) & 0x0F;
|
||||
|
||||
switch (sku_info->revision) {
|
||||
case TEGRA_REVISION_A01:
|
||||
|
|
|
|||
|
|
@ -94,8 +94,8 @@ void __init tegra_init_revision(void)
|
|||
rev = TEGRA_REVISION_A02;
|
||||
break;
|
||||
case 3:
|
||||
if (chip_id == TEGRA20 && (tegra20_spare_fuse_early(18) ||
|
||||
tegra20_spare_fuse_early(19)))
|
||||
if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
|
||||
tegra_fuse_read_spare(19)))
|
||||
rev = TEGRA_REVISION_A03p;
|
||||
else
|
||||
rev = TEGRA_REVISION_A03;
|
||||
|
|
@ -109,10 +109,7 @@ void __init tegra_init_revision(void)
|
|||
|
||||
tegra_sku_info.revision = rev;
|
||||
|
||||
if (chip_id == TEGRA20)
|
||||
tegra_sku_info.sku_id = tegra20_fuse_early(FUSE_SKU_INFO);
|
||||
else
|
||||
tegra_sku_info.sku_id = tegra30_fuse_readl(FUSE_SKU_INFO);
|
||||
tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
|
||||
}
|
||||
|
||||
void __init tegra_init_apbmisc(void)
|
||||
|
|
|
|||
Loading…
Reference in a new issue