From 7eb1afc9765d07c9036b1ad9e7c03e5bd1a58a2b Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 5 Feb 2009 20:45:28 -0700 Subject: [PATCH] [ARM] OMAP3 powerdomains: make USBTLL SAR only available on ES3.1 and beyond Richard Woodruff writes that chip errata prevent USBTLL SAR from working on OMAP3 ES levels before ES3.1: http://marc.info/?l=linux-arm-kernel&m=123319614808833&w=2 Update the OMAP3 powerdomain structures appropriately. Signed-off-by: Paul Walmsley Cc: Richard Woodruff Signed-off-by: Russell King --- arch/arm/mach-omap2/powerdomains.h | 3 ++- arch/arm/mach-omap2/powerdomains34xx.h | 25 +++++++++++++++++++++++-- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h index 1329443f2cd5..691470ea4c6a 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains.h @@ -171,7 +171,8 @@ static struct powerdomain *powerdomains_omap[] __initdata = { &iva2_pwrdm, &mpu_34xx_pwrdm, &neon_pwrdm, - &core_34xx_pwrdm, + &core_34xx_pre_es3_1_pwrdm, + &core_34xx_es3_1_pwrdm, &cam_pwrdm, &dss_pwrdm, &per_pwrdm, diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index 78acfce8bbdc..4dcf94b800ab 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h @@ -200,10 +200,12 @@ static struct powerdomain mpu_34xx_pwrdm = { }; /* No wkdeps or sleepdeps for 34xx core apparently */ -static struct powerdomain core_34xx_pwrdm = { +static struct powerdomain core_34xx_pre_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_IS_OMAP3430ES2 | + CHIP_IS_OMAP3430ES3_0), .pwrsts = PWRSTS_OFF_RET_ON, .dep_bit = OMAP3430_EN_CORE_SHIFT, .banks = 2, @@ -217,6 +219,25 @@ static struct powerdomain core_34xx_pwrdm = { }, }; +/* No wkdeps or sleepdeps for 34xx core apparently */ +static struct powerdomain core_34xx_es3_1_pwrdm = { + .name = "core_pwrdm", + .prcm_offs = CORE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), + .pwrsts = PWRSTS_OFF_RET_ON, + .dep_bit = OMAP3430_EN_CORE_SHIFT, + .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ + [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ + [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ + }, +}; + /* Another case of bit name collisions between several registers: EN_DSS */ static struct powerdomain dss_pwrdm = { .name = "dss_pwrdm",