Merge branch 'at91-3.4-base2+cleanup' of git://github.com/at91linux/linux-at91 into at91/staging/base2+cleanup
* 'at91-3.4-base2+cleanup' of git://github.com/at91linux/linux-at91: (20 commits) ARM: at91: properly sort dtb files in Makefile.boot ARM: at91: add at91sam9g25ek.dts in Makefile.boot ARM: at91/board-dt: drop default console Atmel: move console default platform_device to serial driver ARM: at91: merge SRAM Memory banks thanks to mirroring ARM: at91: finally drop at91_sys_read/write ARM: at91/rtc-at91sam9: pass the GPBR to use via resources ARM: at91:rtc/rtc-at91sam9: ioremap register bank ARM: at91/rtc-at91sam9: each SoC can select the RTT device to use ARM: at91/PMC: make register base soc independent ARM: at91/PMC: move assignment out of printf ARM: at91/pm_slowclock: add runtime detection of memory contoller ARM: at91: make sdram/ddr register base soc independent ARM: at91: move at91rm9200 sdramc defines to at91rm9200_sdramc.h ARM: at91/pm_slowclock: function slow_clock() accepts parameters ARM: at91/pm_slowclock: rename register to named define ARM: at91/ST: remove not needed casts ARM: at91: make ST (System Timer) soc independent ARM: at91: make matrix register base soc independent ARM: at91/at91x40: remove use of at91_sys_read/write Based on top of the at91/9x5, rmk/for-armsoc, at91/device-board, at91/pm_cleanup and at91/base. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
7eca30aef7
|
@ -510,17 +510,3 @@ Why: The pci_scan_bus_parented() interface creates a new root bus. The
|
||||||
convert to using pci_scan_root_bus() so they can supply a list of
|
convert to using pci_scan_root_bus() so they can supply a list of
|
||||||
bus resources when the bus is created.
|
bus resources when the bus is created.
|
||||||
Who: Bjorn Helgaas <bhelgaas@google.com>
|
Who: Bjorn Helgaas <bhelgaas@google.com>
|
||||||
|
|
||||||
----------------------------
|
|
||||||
|
|
||||||
What: The CAP9 SoC family will be removed
|
|
||||||
When: 3.4
|
|
||||||
Files: arch/arm/mach-at91/at91cap9.c
|
|
||||||
arch/arm/mach-at91/at91cap9_devices.c
|
|
||||||
arch/arm/mach-at91/include/mach/at91cap9.h
|
|
||||||
arch/arm/mach-at91/include/mach/at91cap9_matrix.h
|
|
||||||
arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
|
|
||||||
arch/arm/mach-at91/board-cap9adk.c
|
|
||||||
Why: The code is not actively maintained and platforms are now hard to find.
|
|
||||||
Who: Nicolas Ferre <nicolas.ferre@atmel.com>
|
|
||||||
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
|
||||||
|
|
|
@ -324,7 +324,7 @@ config ARCH_AT91
|
||||||
select CLKDEV_LOOKUP
|
select CLKDEV_LOOKUP
|
||||||
help
|
help
|
||||||
This enables support for systems based on the Atmel AT91RM9200,
|
This enables support for systems based on the Atmel AT91RM9200,
|
||||||
AT91SAM9 and AT91CAP9 processors.
|
AT91SAM9 processors.
|
||||||
|
|
||||||
config ARCH_BCMRING
|
config ARCH_BCMRING
|
||||||
bool "Broadcom BCMRING"
|
bool "Broadcom BCMRING"
|
||||||
|
|
|
@ -81,47 +81,14 @@ choice
|
||||||
prompt "Kernel low-level debugging port"
|
prompt "Kernel low-level debugging port"
|
||||||
depends on DEBUG_LL
|
depends on DEBUG_LL
|
||||||
|
|
||||||
config DEBUG_LL_UART_NONE
|
|
||||||
bool "No low-level debugging UART"
|
|
||||||
help
|
|
||||||
Say Y here if your platform doesn't provide a UART option
|
|
||||||
below. This relies on your platform choosing the right UART
|
|
||||||
definition internally in order for low-level debugging to
|
|
||||||
work.
|
|
||||||
|
|
||||||
config DEBUG_ICEDCC
|
|
||||||
bool "Kernel low-level debugging via EmbeddedICE DCC channel"
|
|
||||||
help
|
|
||||||
Say Y here if you want the debug print routines to direct
|
|
||||||
their output to the EmbeddedICE macrocell's DCC channel using
|
|
||||||
co-processor 14. This is known to work on the ARM9 style ICE
|
|
||||||
channel and on the XScale with the PEEDI.
|
|
||||||
|
|
||||||
Note that the system will appear to hang during boot if there
|
|
||||||
is nothing connected to read from the DCC.
|
|
||||||
|
|
||||||
config AT91_DEBUG_LL_DBGU0
|
config AT91_DEBUG_LL_DBGU0
|
||||||
bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
|
bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
|
||||||
depends on HAVE_AT91_DBGU0
|
depends on HAVE_AT91_DBGU0
|
||||||
|
|
||||||
config AT91_DEBUG_LL_DBGU1
|
config AT91_DEBUG_LL_DBGU1
|
||||||
bool "Kernel low-level debugging on 9263, 9g45 and cap9"
|
bool "Kernel low-level debugging on 9263 and 9g45"
|
||||||
depends on HAVE_AT91_DBGU1
|
depends on HAVE_AT91_DBGU1
|
||||||
|
|
||||||
config DEBUG_FOOTBRIDGE_COM1
|
|
||||||
bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
|
|
||||||
depends on FOOTBRIDGE
|
|
||||||
help
|
|
||||||
Say Y here if you want the debug print routines to direct
|
|
||||||
their output to the 8250 at PCI COM1.
|
|
||||||
|
|
||||||
config DEBUG_DC21285_PORT
|
|
||||||
bool "Kernel low-level debugging messages via footbridge serial port"
|
|
||||||
depends on FOOTBRIDGE
|
|
||||||
help
|
|
||||||
Say Y here if you want the debug print routines to direct
|
|
||||||
their output to the serial port in the DC21285 (Footbridge).
|
|
||||||
|
|
||||||
config DEBUG_CLPS711X_UART1
|
config DEBUG_CLPS711X_UART1
|
||||||
bool "Kernel low-level debugging messages via UART1"
|
bool "Kernel low-level debugging messages via UART1"
|
||||||
depends on ARCH_CLPS711X
|
depends on ARCH_CLPS711X
|
||||||
|
@ -136,6 +103,20 @@ choice
|
||||||
Say Y here if you want the debug print routines to direct
|
Say Y here if you want the debug print routines to direct
|
||||||
their output to the second serial port on these devices.
|
their output to the second serial port on these devices.
|
||||||
|
|
||||||
|
config DEBUG_DC21285_PORT
|
||||||
|
bool "Kernel low-level debugging messages via footbridge serial port"
|
||||||
|
depends on FOOTBRIDGE
|
||||||
|
help
|
||||||
|
Say Y here if you want the debug print routines to direct
|
||||||
|
their output to the serial port in the DC21285 (Footbridge).
|
||||||
|
|
||||||
|
config DEBUG_FOOTBRIDGE_COM1
|
||||||
|
bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
|
||||||
|
depends on FOOTBRIDGE
|
||||||
|
help
|
||||||
|
Say Y here if you want the debug print routines to direct
|
||||||
|
their output to the 8250 at PCI COM1.
|
||||||
|
|
||||||
config DEBUG_HIGHBANK_UART
|
config DEBUG_HIGHBANK_UART
|
||||||
bool "Kernel low-level debugging messages via Highbank UART"
|
bool "Kernel low-level debugging messages via Highbank UART"
|
||||||
depends on ARCH_HIGHBANK
|
depends on ARCH_HIGHBANK
|
||||||
|
@ -206,55 +187,6 @@ choice
|
||||||
Say Y here if you want kernel low-level debugging support
|
Say Y here if you want kernel low-level debugging support
|
||||||
on i.MX6Q.
|
on i.MX6Q.
|
||||||
|
|
||||||
config DEBUG_S3C_UART0
|
|
||||||
depends on PLAT_SAMSUNG
|
|
||||||
bool "Use S3C UART 0 for low-level debug"
|
|
||||||
help
|
|
||||||
Say Y here if you want the debug print routines to direct
|
|
||||||
their output to UART 0. The port must have been initialised
|
|
||||||
by the boot-loader before use.
|
|
||||||
|
|
||||||
The uncompressor code port configuration is now handled
|
|
||||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
|
||||||
|
|
||||||
config DEBUG_S3C_UART1
|
|
||||||
depends on PLAT_SAMSUNG
|
|
||||||
bool "Use S3C UART 1 for low-level debug"
|
|
||||||
help
|
|
||||||
Say Y here if you want the debug print routines to direct
|
|
||||||
their output to UART 1. The port must have been initialised
|
|
||||||
by the boot-loader before use.
|
|
||||||
|
|
||||||
The uncompressor code port configuration is now handled
|
|
||||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
|
||||||
|
|
||||||
config DEBUG_S3C_UART2
|
|
||||||
depends on PLAT_SAMSUNG
|
|
||||||
bool "Use S3C UART 2 for low-level debug"
|
|
||||||
help
|
|
||||||
Say Y here if you want the debug print routines to direct
|
|
||||||
their output to UART 2. The port must have been initialised
|
|
||||||
by the boot-loader before use.
|
|
||||||
|
|
||||||
The uncompressor code port configuration is now handled
|
|
||||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
|
||||||
|
|
||||||
config DEBUG_REALVIEW_STD_PORT
|
|
||||||
bool "RealView Default UART"
|
|
||||||
depends on ARCH_REALVIEW
|
|
||||||
help
|
|
||||||
Say Y here if you want the debug print routines to direct
|
|
||||||
their output to the serial port on RealView EB, PB11MP, PBA8
|
|
||||||
and PBX platforms.
|
|
||||||
|
|
||||||
config DEBUG_REALVIEW_PB1176_PORT
|
|
||||||
bool "RealView PB1176 UART"
|
|
||||||
depends on MACH_REALVIEW_PB1176
|
|
||||||
help
|
|
||||||
Say Y here if you want the debug print routines to direct
|
|
||||||
their output to the standard serial port on the RealView
|
|
||||||
PB1176 platform.
|
|
||||||
|
|
||||||
config DEBUG_MSM_UART1
|
config DEBUG_MSM_UART1
|
||||||
bool "Kernel low-level debugging messages via MSM UART1"
|
bool "Kernel low-level debugging messages via MSM UART1"
|
||||||
depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
|
depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
|
||||||
|
@ -292,6 +224,74 @@ choice
|
||||||
Say Y here if you want the debug print routines to direct
|
Say Y here if you want the debug print routines to direct
|
||||||
their output to the serial port on MSM 8960 devices.
|
their output to the serial port on MSM 8960 devices.
|
||||||
|
|
||||||
|
config DEBUG_REALVIEW_STD_PORT
|
||||||
|
bool "RealView Default UART"
|
||||||
|
depends on ARCH_REALVIEW
|
||||||
|
help
|
||||||
|
Say Y here if you want the debug print routines to direct
|
||||||
|
their output to the serial port on RealView EB, PB11MP, PBA8
|
||||||
|
and PBX platforms.
|
||||||
|
|
||||||
|
config DEBUG_REALVIEW_PB1176_PORT
|
||||||
|
bool "RealView PB1176 UART"
|
||||||
|
depends on MACH_REALVIEW_PB1176
|
||||||
|
help
|
||||||
|
Say Y here if you want the debug print routines to direct
|
||||||
|
their output to the standard serial port on the RealView
|
||||||
|
PB1176 platform.
|
||||||
|
|
||||||
|
config DEBUG_S3C_UART0
|
||||||
|
depends on PLAT_SAMSUNG
|
||||||
|
bool "Use S3C UART 0 for low-level debug"
|
||||||
|
help
|
||||||
|
Say Y here if you want the debug print routines to direct
|
||||||
|
their output to UART 0. The port must have been initialised
|
||||||
|
by the boot-loader before use.
|
||||||
|
|
||||||
|
The uncompressor code port configuration is now handled
|
||||||
|
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||||
|
|
||||||
|
config DEBUG_S3C_UART1
|
||||||
|
depends on PLAT_SAMSUNG
|
||||||
|
bool "Use S3C UART 1 for low-level debug"
|
||||||
|
help
|
||||||
|
Say Y here if you want the debug print routines to direct
|
||||||
|
their output to UART 1. The port must have been initialised
|
||||||
|
by the boot-loader before use.
|
||||||
|
|
||||||
|
The uncompressor code port configuration is now handled
|
||||||
|
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||||
|
|
||||||
|
config DEBUG_S3C_UART2
|
||||||
|
depends on PLAT_SAMSUNG
|
||||||
|
bool "Use S3C UART 2 for low-level debug"
|
||||||
|
help
|
||||||
|
Say Y here if you want the debug print routines to direct
|
||||||
|
their output to UART 2. The port must have been initialised
|
||||||
|
by the boot-loader before use.
|
||||||
|
|
||||||
|
The uncompressor code port configuration is now handled
|
||||||
|
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||||
|
|
||||||
|
config DEBUG_LL_UART_NONE
|
||||||
|
bool "No low-level debugging UART"
|
||||||
|
help
|
||||||
|
Say Y here if your platform doesn't provide a UART option
|
||||||
|
below. This relies on your platform choosing the right UART
|
||||||
|
definition internally in order for low-level debugging to
|
||||||
|
work.
|
||||||
|
|
||||||
|
config DEBUG_ICEDCC
|
||||||
|
bool "Kernel low-level debugging via EmbeddedICE DCC channel"
|
||||||
|
help
|
||||||
|
Say Y here if you want the debug print routines to direct
|
||||||
|
their output to the EmbeddedICE macrocell's DCC channel using
|
||||||
|
co-processor 14. This is known to work on the ARM9 style ICE
|
||||||
|
channel and on the XScale with the PEEDI.
|
||||||
|
|
||||||
|
Note that the system will appear to hang during boot if there
|
||||||
|
is nothing connected to read from the DCC.
|
||||||
|
|
||||||
endchoice
|
endchoice
|
||||||
|
|
||||||
config EARLY_PRINTK
|
config EARLY_PRINTK
|
||||||
|
|
37
arch/arm/boot/dts/at91sam9g25ek.dts
Normal file
37
arch/arm/boot/dts/at91sam9g25ek.dts
Normal file
|
@ -0,0 +1,37 @@
|
||||||
|
/*
|
||||||
|
* at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Atmel,
|
||||||
|
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
/dts-v1/;
|
||||||
|
/include/ "at91sam9x5.dtsi"
|
||||||
|
/include/ "at91sam9x5cm.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Atmel AT91SAM9G25-EK";
|
||||||
|
compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
|
||||||
|
};
|
||||||
|
|
||||||
|
ahb {
|
||||||
|
apb {
|
||||||
|
dbgu: serial@fffff200 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart0: serial@f801c000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
macb0: ethernet@f802c000 {
|
||||||
|
phy-mode = "rmii";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
172
arch/arm/boot/dts/at91sam9x5.dtsi
Normal file
172
arch/arm/boot/dts/at91sam9x5.dtsi
Normal file
|
@ -0,0 +1,172 @@
|
||||||
|
/*
|
||||||
|
* at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
|
||||||
|
* applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
|
||||||
|
* AT91SAM9X25, AT91SAM9X35 SoC
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Atmel,
|
||||||
|
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/include/ "skeleton.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Atmel AT91SAM9x5 family SoC";
|
||||||
|
compatible = "atmel,at91sam9x5";
|
||||||
|
interrupt-parent = <&aic>;
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &dbgu;
|
||||||
|
serial1 = &usart0;
|
||||||
|
serial2 = &usart1;
|
||||||
|
serial3 = &usart2;
|
||||||
|
gpio0 = &pioA;
|
||||||
|
gpio1 = &pioB;
|
||||||
|
gpio2 = &pioC;
|
||||||
|
gpio3 = &pioD;
|
||||||
|
tcb0 = &tcb0;
|
||||||
|
tcb1 = &tcb1;
|
||||||
|
};
|
||||||
|
cpus {
|
||||||
|
cpu@0 {
|
||||||
|
compatible = "arm,arm926ejs";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@20000000 {
|
||||||
|
reg = <0x20000000 0x10000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ahb {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
apb {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
aic: interrupt-controller@fffff000 {
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
compatible = "atmel,at91rm9200-aic";
|
||||||
|
interrupt-controller;
|
||||||
|
interrupt-parent;
|
||||||
|
reg = <0xfffff000 0x200>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pit: timer@fffffe30 {
|
||||||
|
compatible = "atmel,at91sam9260-pit";
|
||||||
|
reg = <0xfffffe30 0xf>;
|
||||||
|
interrupts = <1 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
tcb0: timer@f8008000 {
|
||||||
|
compatible = "atmel,at91sam9x5-tcb";
|
||||||
|
reg = <0xf8008000 0x100>;
|
||||||
|
interrupts = <17 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
tcb1: timer@f800c000 {
|
||||||
|
compatible = "atmel,at91sam9x5-tcb";
|
||||||
|
reg = <0xf800c000 0x100>;
|
||||||
|
interrupts = <17 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma0: dma-controller@ffffec00 {
|
||||||
|
compatible = "atmel,at91sam9g45-dma";
|
||||||
|
reg = <0xffffec00 0x200>;
|
||||||
|
interrupts = <20 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma1: dma-controller@ffffee00 {
|
||||||
|
compatible = "atmel,at91sam9g45-dma";
|
||||||
|
reg = <0xffffee00 0x200>;
|
||||||
|
interrupts = <21 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pioA: gpio@fffff400 {
|
||||||
|
compatible = "atmel,at91rm9200-gpio";
|
||||||
|
reg = <0xfffff400 0x100>;
|
||||||
|
interrupts = <2 4>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
pioB: gpio@fffff600 {
|
||||||
|
compatible = "atmel,at91rm9200-gpio";
|
||||||
|
reg = <0xfffff600 0x100>;
|
||||||
|
interrupts = <2 4>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
pioC: gpio@fffff800 {
|
||||||
|
compatible = "atmel,at91rm9200-gpio";
|
||||||
|
reg = <0xfffff800 0x100>;
|
||||||
|
interrupts = <3 4>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
pioD: gpio@fffffa00 {
|
||||||
|
compatible = "atmel,at91rm9200-gpio";
|
||||||
|
reg = <0xfffffa00 0x100>;
|
||||||
|
interrupts = <3 4>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
dbgu: serial@fffff200 {
|
||||||
|
compatible = "atmel,at91sam9260-usart";
|
||||||
|
reg = <0xfffff200 0x200>;
|
||||||
|
interrupts = <1 4>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart0: serial@f801c000 {
|
||||||
|
compatible = "atmel,at91sam9260-usart";
|
||||||
|
reg = <0xf801c000 0x200>;
|
||||||
|
interrupts = <5 4>;
|
||||||
|
atmel,use-dma-rx;
|
||||||
|
atmel,use-dma-tx;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart1: serial@f8020000 {
|
||||||
|
compatible = "atmel,at91sam9260-usart";
|
||||||
|
reg = <0xf8020000 0x200>;
|
||||||
|
interrupts = <6 4>;
|
||||||
|
atmel,use-dma-rx;
|
||||||
|
atmel,use-dma-tx;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart2: serial@f8024000 {
|
||||||
|
compatible = "atmel,at91sam9260-usart";
|
||||||
|
reg = <0xf8024000 0x200>;
|
||||||
|
interrupts = <7 4>;
|
||||||
|
atmel,use-dma-rx;
|
||||||
|
atmel,use-dma-tx;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
macb0: ethernet@f802c000 {
|
||||||
|
compatible = "cdns,at32ap7000-macb", "cdns,macb";
|
||||||
|
reg = <0xf802c000 0x100>;
|
||||||
|
interrupts = <24 4>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
macb1: ethernet@f8030000 {
|
||||||
|
compatible = "cdns,at32ap7000-macb", "cdns,macb";
|
||||||
|
reg = <0xf8030000 0x100>;
|
||||||
|
interrupts = <27 4>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
14
arch/arm/boot/dts/at91sam9x5cm.dtsi
Normal file
14
arch/arm/boot/dts/at91sam9x5cm.dtsi
Normal file
|
@ -0,0 +1,14 @@
|
||||||
|
/*
|
||||||
|
* at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Atmel,
|
||||||
|
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/ {
|
||||||
|
memory@20000000 {
|
||||||
|
reg = <0x20000000 0x8000000>;
|
||||||
|
};
|
||||||
|
};
|
|
@ -1,108 +0,0 @@
|
||||||
CONFIG_EXPERIMENTAL=y
|
|
||||||
# CONFIG_LOCALVERSION_AUTO is not set
|
|
||||||
# CONFIG_SWAP is not set
|
|
||||||
CONFIG_SYSVIPC=y
|
|
||||||
CONFIG_LOG_BUF_SHIFT=14
|
|
||||||
CONFIG_BLK_DEV_INITRD=y
|
|
||||||
CONFIG_SLAB=y
|
|
||||||
CONFIG_MODULES=y
|
|
||||||
CONFIG_MODULE_UNLOAD=y
|
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
|
||||||
# CONFIG_IOSCHED_DEADLINE is not set
|
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
|
||||||
CONFIG_ARCH_AT91=y
|
|
||||||
CONFIG_ARCH_AT91CAP9=y
|
|
||||||
CONFIG_MACH_AT91CAP9ADK=y
|
|
||||||
CONFIG_MTD_AT91_DATAFLASH_CARD=y
|
|
||||||
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
|
|
||||||
# CONFIG_ARM_THUMB is not set
|
|
||||||
CONFIG_AEABI=y
|
|
||||||
CONFIG_LEDS=y
|
|
||||||
CONFIG_LEDS_CPU=y
|
|
||||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
|
||||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
|
||||||
CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/ram0 rw"
|
|
||||||
CONFIG_FPE_NWFPE=y
|
|
||||||
CONFIG_NET=y
|
|
||||||
CONFIG_PACKET=y
|
|
||||||
CONFIG_UNIX=y
|
|
||||||
CONFIG_INET=y
|
|
||||||
CONFIG_IP_PNP=y
|
|
||||||
CONFIG_IP_PNP_BOOTP=y
|
|
||||||
CONFIG_IP_PNP_RARP=y
|
|
||||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
|
||||||
# CONFIG_INET_LRO is not set
|
|
||||||
# CONFIG_INET_DIAG is not set
|
|
||||||
# CONFIG_IPV6 is not set
|
|
||||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
|
||||||
CONFIG_MTD=y
|
|
||||||
CONFIG_MTD_CMDLINE_PARTS=y
|
|
||||||
CONFIG_MTD_CHAR=y
|
|
||||||
CONFIG_MTD_BLOCK=y
|
|
||||||
CONFIG_MTD_CFI=y
|
|
||||||
CONFIG_MTD_JEDECPROBE=y
|
|
||||||
CONFIG_MTD_CFI_AMDSTD=y
|
|
||||||
CONFIG_MTD_PHYSMAP=y
|
|
||||||
CONFIG_MTD_DATAFLASH=y
|
|
||||||
CONFIG_MTD_NAND=y
|
|
||||||
CONFIG_MTD_NAND_ATMEL=y
|
|
||||||
CONFIG_BLK_DEV_LOOP=y
|
|
||||||
CONFIG_BLK_DEV_RAM=y
|
|
||||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
|
||||||
CONFIG_SCSI=y
|
|
||||||
CONFIG_BLK_DEV_SD=y
|
|
||||||
CONFIG_SCSI_MULTI_LUN=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_MACB=y
|
|
||||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
|
||||||
CONFIG_INPUT_EVDEV=y
|
|
||||||
# CONFIG_INPUT_KEYBOARD is not set
|
|
||||||
# CONFIG_INPUT_MOUSE is not set
|
|
||||||
CONFIG_INPUT_TOUCHSCREEN=y
|
|
||||||
CONFIG_TOUCHSCREEN_ADS7846=y
|
|
||||||
# CONFIG_SERIO is not set
|
|
||||||
CONFIG_SERIAL_ATMEL=y
|
|
||||||
CONFIG_SERIAL_ATMEL_CONSOLE=y
|
|
||||||
CONFIG_HW_RANDOM=y
|
|
||||||
CONFIG_I2C=y
|
|
||||||
CONFIG_I2C_CHARDEV=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_SPI_ATMEL=y
|
|
||||||
# CONFIG_HWMON is not set
|
|
||||||
CONFIG_WATCHDOG=y
|
|
||||||
CONFIG_WATCHDOG_NOWAYOUT=y
|
|
||||||
CONFIG_FB=y
|
|
||||||
CONFIG_FB_ATMEL=y
|
|
||||||
CONFIG_LOGO=y
|
|
||||||
# CONFIG_LOGO_LINUX_MONO is not set
|
|
||||||
# CONFIG_LOGO_LINUX_CLUT224 is not set
|
|
||||||
# CONFIG_USB_HID is not set
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_DEVICEFS=y
|
|
||||||
CONFIG_USB_MON=y
|
|
||||||
CONFIG_USB_OHCI_HCD=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_USB_GADGET=y
|
|
||||||
CONFIG_USB_ETH=m
|
|
||||||
CONFIG_USB_FILE_STORAGE=m
|
|
||||||
CONFIG_MMC=y
|
|
||||||
CONFIG_MMC_AT91=m
|
|
||||||
CONFIG_RTC_CLASS=y
|
|
||||||
CONFIG_RTC_DRV_AT91SAM9=y
|
|
||||||
CONFIG_EXT2_FS=y
|
|
||||||
CONFIG_VFAT_FS=y
|
|
||||||
CONFIG_TMPFS=y
|
|
||||||
CONFIG_JFFS2_FS=y
|
|
||||||
CONFIG_CRAMFS=y
|
|
||||||
CONFIG_NFS_FS=y
|
|
||||||
CONFIG_ROOT_NFS=y
|
|
||||||
CONFIG_NLS_CODEPAGE_437=y
|
|
||||||
CONFIG_NLS_CODEPAGE_850=y
|
|
||||||
CONFIG_NLS_ISO8859_1=y
|
|
||||||
CONFIG_DEBUG_FS=y
|
|
||||||
CONFIG_DEBUG_KERNEL=y
|
|
||||||
CONFIG_DEBUG_INFO=y
|
|
||||||
CONFIG_DEBUG_USER=y
|
|
|
@ -110,6 +110,7 @@ extern void cpu_init(void);
|
||||||
|
|
||||||
void soft_restart(unsigned long);
|
void soft_restart(unsigned long);
|
||||||
extern void (*arm_pm_restart)(char str, const char *cmd);
|
extern void (*arm_pm_restart)(char str, const char *cmd);
|
||||||
|
extern void (*arm_pm_idle)(void);
|
||||||
|
|
||||||
#define UDBG_UNDEFINED (1 << 0)
|
#define UDBG_UNDEFINED (1 << 0)
|
||||||
#define UDBG_SYSCALL (1 << 1)
|
#define UDBG_SYSCALL (1 << 1)
|
||||||
|
|
|
@ -61,8 +61,6 @@ extern void setup_mm_for_reboot(void);
|
||||||
|
|
||||||
static volatile int hlt_counter;
|
static volatile int hlt_counter;
|
||||||
|
|
||||||
#include <mach/system.h>
|
|
||||||
|
|
||||||
void disable_hlt(void)
|
void disable_hlt(void)
|
||||||
{
|
{
|
||||||
hlt_counter++;
|
hlt_counter++;
|
||||||
|
@ -181,13 +179,17 @@ void cpu_idle_wait(void)
|
||||||
EXPORT_SYMBOL_GPL(cpu_idle_wait);
|
EXPORT_SYMBOL_GPL(cpu_idle_wait);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This is our default idle handler. We need to disable
|
* This is our default idle handler.
|
||||||
* interrupts here to ensure we don't miss a wakeup call.
|
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
void (*arm_pm_idle)(void);
|
||||||
|
|
||||||
static void default_idle(void)
|
static void default_idle(void)
|
||||||
{
|
{
|
||||||
if (!need_resched())
|
if (arm_pm_idle)
|
||||||
arch_idle();
|
arm_pm_idle();
|
||||||
|
else
|
||||||
|
cpu_do_idle();
|
||||||
local_irq_enable();
|
local_irq_enable();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -215,6 +217,10 @@ void cpu_idle(void)
|
||||||
cpu_die();
|
cpu_die();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We need to disable interrupts here
|
||||||
|
* to ensure we don't miss a wakeup call.
|
||||||
|
*/
|
||||||
local_irq_disable();
|
local_irq_disable();
|
||||||
#ifdef CONFIG_PL310_ERRATA_769419
|
#ifdef CONFIG_PL310_ERRATA_769419
|
||||||
wmb();
|
wmb();
|
||||||
|
@ -222,19 +228,18 @@ void cpu_idle(void)
|
||||||
if (hlt_counter) {
|
if (hlt_counter) {
|
||||||
local_irq_enable();
|
local_irq_enable();
|
||||||
cpu_relax();
|
cpu_relax();
|
||||||
} else {
|
} else if (!need_resched()) {
|
||||||
stop_critical_timings();
|
stop_critical_timings();
|
||||||
if (cpuidle_idle_call())
|
if (cpuidle_idle_call())
|
||||||
pm_idle();
|
pm_idle();
|
||||||
start_critical_timings();
|
start_critical_timings();
|
||||||
/*
|
/*
|
||||||
* This will eventually be removed - pm_idle
|
* pm_idle functions must always
|
||||||
* functions should always return with IRQs
|
* return with IRQs enabled.
|
||||||
* enabled.
|
|
||||||
*/
|
*/
|
||||||
WARN_ON(irqs_disabled());
|
WARN_ON(irqs_disabled());
|
||||||
|
} else
|
||||||
local_irq_enable();
|
local_irq_enable();
|
||||||
}
|
|
||||||
}
|
}
|
||||||
leds_event(led_idle_end);
|
leds_event(led_idle_end);
|
||||||
rcu_idle_exit();
|
rcu_idle_exit();
|
||||||
|
|
|
@ -102,13 +102,13 @@ config ARCH_AT91SAM9G45
|
||||||
select HAVE_AT91_DBGU1
|
select HAVE_AT91_DBGU1
|
||||||
select AT91_SAM9G45_RESET
|
select AT91_SAM9G45_RESET
|
||||||
|
|
||||||
config ARCH_AT91CAP9
|
config ARCH_AT91SAM9X5
|
||||||
bool "AT91CAP9"
|
bool "AT91SAM9x5 family"
|
||||||
select CPU_ARM926T
|
select CPU_ARM926T
|
||||||
select GENERIC_CLOCKEVENTS
|
select GENERIC_CLOCKEVENTS
|
||||||
select HAVE_FB_ATMEL
|
select HAVE_FB_ATMEL
|
||||||
select HAVE_NET_MACB
|
select HAVE_NET_MACB
|
||||||
select HAVE_AT91_DBGU1
|
select HAVE_AT91_DBGU0
|
||||||
select AT91_SAM9G45_RESET
|
select AT91_SAM9G45_RESET
|
||||||
|
|
||||||
config ARCH_AT91X40
|
config ARCH_AT91X40
|
||||||
|
@ -447,21 +447,6 @@ endif
|
||||||
|
|
||||||
# ----------------------------------------------------------
|
# ----------------------------------------------------------
|
||||||
|
|
||||||
if ARCH_AT91CAP9
|
|
||||||
|
|
||||||
comment "AT91CAP9 Board Type"
|
|
||||||
|
|
||||||
config MACH_AT91CAP9ADK
|
|
||||||
bool "Atmel AT91CAP9A-DK Evaluation Kit"
|
|
||||||
select HAVE_AT91_DATAFLASH_CARD
|
|
||||||
help
|
|
||||||
Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
|
|
||||||
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
||||||
# ----------------------------------------------------------
|
|
||||||
|
|
||||||
if ARCH_AT91X40
|
if ARCH_AT91X40
|
||||||
|
|
||||||
comment "AT91X40 Board Type"
|
comment "AT91X40 Board Type"
|
||||||
|
@ -544,7 +529,7 @@ config AT91_EARLY_DBGU0
|
||||||
depends on HAVE_AT91_DBGU0
|
depends on HAVE_AT91_DBGU0
|
||||||
|
|
||||||
config AT91_EARLY_DBGU1
|
config AT91_EARLY_DBGU1
|
||||||
bool "DBGU on 9263, 9g45 and cap9"
|
bool "DBGU on 9263 and 9g45"
|
||||||
depends on HAVE_AT91_DBGU1
|
depends on HAVE_AT91_DBGU1
|
||||||
|
|
||||||
config AT91_EARLY_USART0
|
config AT91_EARLY_USART0
|
||||||
|
|
|
@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_d
|
||||||
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
|
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
|
||||||
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||||
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
|
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
|
||||||
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
|
obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o
|
||||||
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
|
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
|
||||||
|
|
||||||
# AT91RM9200 board-specific support
|
# AT91RM9200 board-specific support
|
||||||
|
@ -81,9 +81,6 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
|
||||||
# AT91SAM board with device-tree
|
# AT91SAM board with device-tree
|
||||||
obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
|
obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
|
||||||
|
|
||||||
# AT91CAP9 board-specific support
|
|
||||||
obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
|
|
||||||
|
|
||||||
# AT91X40 board-specific support
|
# AT91X40 board-specific support
|
||||||
obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
|
obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
|
||||||
|
|
||||||
|
|
|
@ -3,11 +3,7 @@
|
||||||
# PARAMS_PHYS must be within 4MB of ZRELADDR
|
# PARAMS_PHYS must be within 4MB of ZRELADDR
|
||||||
# INITRD_PHYS must be in RAM
|
# INITRD_PHYS must be in RAM
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_AT91CAP9),y)
|
ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
|
||||||
zreladdr-y += 0x70008000
|
|
||||||
params_phys-y := 0x70000100
|
|
||||||
initrd_phys-y := 0x70410000
|
|
||||||
else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
|
|
||||||
zreladdr-y += 0x70008000
|
zreladdr-y += 0x70008000
|
||||||
params_phys-y := 0x70000100
|
params_phys-y := 0x70000100
|
||||||
initrd_phys-y := 0x70410000
|
initrd_phys-y := 0x70410000
|
||||||
|
@ -17,4 +13,10 @@ params_phys-y := 0x20000100
|
||||||
initrd_phys-y := 0x20410000
|
initrd_phys-y := 0x20410000
|
||||||
endif
|
endif
|
||||||
|
|
||||||
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
|
# Keep dtb files sorted alphabetically for each SoC
|
||||||
|
# sam9g20
|
||||||
|
dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
|
||||||
|
# sam9g45
|
||||||
|
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
|
||||||
|
# sam9x5
|
||||||
|
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
|
||||||
|
|
|
@ -1,396 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-at91/at91cap9.c
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Atmel Corporation.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/module.h>
|
|
||||||
|
|
||||||
#include <asm/irq.h>
|
|
||||||
#include <asm/mach/arch.h>
|
|
||||||
#include <asm/mach/map.h>
|
|
||||||
|
|
||||||
#include <mach/cpu.h>
|
|
||||||
#include <mach/at91cap9.h>
|
|
||||||
#include <mach/at91_pmc.h>
|
|
||||||
|
|
||||||
#include "soc.h"
|
|
||||||
#include "generic.h"
|
|
||||||
#include "clock.h"
|
|
||||||
#include "sam9_smc.h"
|
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
|
||||||
* Clocks
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The peripheral clocks.
|
|
||||||
*/
|
|
||||||
static struct clk pioABCD_clk = {
|
|
||||||
.name = "pioABCD_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mpb0_clk = {
|
|
||||||
.name = "mpb0_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MPB0,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mpb1_clk = {
|
|
||||||
.name = "mpb1_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MPB1,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mpb2_clk = {
|
|
||||||
.name = "mpb2_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MPB2,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mpb3_clk = {
|
|
||||||
.name = "mpb3_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MPB3,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mpb4_clk = {
|
|
||||||
.name = "mpb4_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MPB4,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk usart0_clk = {
|
|
||||||
.name = "usart0_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_US0,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk usart1_clk = {
|
|
||||||
.name = "usart1_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_US1,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk usart2_clk = {
|
|
||||||
.name = "usart2_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_US2,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mmc0_clk = {
|
|
||||||
.name = "mci0_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MCI0,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mmc1_clk = {
|
|
||||||
.name = "mci1_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MCI1,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk can_clk = {
|
|
||||||
.name = "can_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_CAN,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk twi_clk = {
|
|
||||||
.name = "twi_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_TWI,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk spi0_clk = {
|
|
||||||
.name = "spi0_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_SPI0,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk spi1_clk = {
|
|
||||||
.name = "spi1_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_SPI1,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk ssc0_clk = {
|
|
||||||
.name = "ssc0_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_SSC0,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk ssc1_clk = {
|
|
||||||
.name = "ssc1_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_SSC1,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk ac97_clk = {
|
|
||||||
.name = "ac97_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_AC97C,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk tcb_clk = {
|
|
||||||
.name = "tcb_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_TCB,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk pwm_clk = {
|
|
||||||
.name = "pwm_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_PWMC,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk macb_clk = {
|
|
||||||
.name = "pclk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_EMAC,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk aestdes_clk = {
|
|
||||||
.name = "aestdes_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_AESTDES,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk adc_clk = {
|
|
||||||
.name = "adc_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_ADC,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk isi_clk = {
|
|
||||||
.name = "isi_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_ISI,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk lcdc_clk = {
|
|
||||||
.name = "lcdc_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_LCDC,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk dma_clk = {
|
|
||||||
.name = "dma_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_DMA,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk udphs_clk = {
|
|
||||||
.name = "udphs_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_UDPHS,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk ohci_clk = {
|
|
||||||
.name = "ohci_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_UHP,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct clk *periph_clocks[] __initdata = {
|
|
||||||
&pioABCD_clk,
|
|
||||||
&mpb0_clk,
|
|
||||||
&mpb1_clk,
|
|
||||||
&mpb2_clk,
|
|
||||||
&mpb3_clk,
|
|
||||||
&mpb4_clk,
|
|
||||||
&usart0_clk,
|
|
||||||
&usart1_clk,
|
|
||||||
&usart2_clk,
|
|
||||||
&mmc0_clk,
|
|
||||||
&mmc1_clk,
|
|
||||||
&can_clk,
|
|
||||||
&twi_clk,
|
|
||||||
&spi0_clk,
|
|
||||||
&spi1_clk,
|
|
||||||
&ssc0_clk,
|
|
||||||
&ssc1_clk,
|
|
||||||
&ac97_clk,
|
|
||||||
&tcb_clk,
|
|
||||||
&pwm_clk,
|
|
||||||
&macb_clk,
|
|
||||||
&aestdes_clk,
|
|
||||||
&adc_clk,
|
|
||||||
&isi_clk,
|
|
||||||
&lcdc_clk,
|
|
||||||
&dma_clk,
|
|
||||||
&udphs_clk,
|
|
||||||
&ohci_clk,
|
|
||||||
// irq0 .. irq1
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct clk_lookup periph_clocks_lookups[] = {
|
|
||||||
/* One additional fake clock for macb_hclk */
|
|
||||||
CLKDEV_CON_ID("hclk", &macb_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
|
|
||||||
/* fake hclk clock */
|
|
||||||
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
|
|
||||||
CLKDEV_CON_ID("pioA", &pioABCD_clk),
|
|
||||||
CLKDEV_CON_ID("pioB", &pioABCD_clk),
|
|
||||||
CLKDEV_CON_ID("pioC", &pioABCD_clk),
|
|
||||||
CLKDEV_CON_ID("pioD", &pioABCD_clk),
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct clk_lookup usart_clocks_lookups[] = {
|
|
||||||
CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
|
|
||||||
CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The four programmable clocks.
|
|
||||||
* You must configure pin multiplexing to bring these signals out.
|
|
||||||
*/
|
|
||||||
static struct clk pck0 = {
|
|
||||||
.name = "pck0",
|
|
||||||
.pmc_mask = AT91_PMC_PCK0,
|
|
||||||
.type = CLK_TYPE_PROGRAMMABLE,
|
|
||||||
.id = 0,
|
|
||||||
};
|
|
||||||
static struct clk pck1 = {
|
|
||||||
.name = "pck1",
|
|
||||||
.pmc_mask = AT91_PMC_PCK1,
|
|
||||||
.type = CLK_TYPE_PROGRAMMABLE,
|
|
||||||
.id = 1,
|
|
||||||
};
|
|
||||||
static struct clk pck2 = {
|
|
||||||
.name = "pck2",
|
|
||||||
.pmc_mask = AT91_PMC_PCK2,
|
|
||||||
.type = CLK_TYPE_PROGRAMMABLE,
|
|
||||||
.id = 2,
|
|
||||||
};
|
|
||||||
static struct clk pck3 = {
|
|
||||||
.name = "pck3",
|
|
||||||
.pmc_mask = AT91_PMC_PCK3,
|
|
||||||
.type = CLK_TYPE_PROGRAMMABLE,
|
|
||||||
.id = 3,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init at91cap9_register_clocks(void)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
|
||||||
clk_register(periph_clocks[i]);
|
|
||||||
|
|
||||||
clkdev_add_table(periph_clocks_lookups,
|
|
||||||
ARRAY_SIZE(periph_clocks_lookups));
|
|
||||||
clkdev_add_table(usart_clocks_lookups,
|
|
||||||
ARRAY_SIZE(usart_clocks_lookups));
|
|
||||||
|
|
||||||
clk_register(&pck0);
|
|
||||||
clk_register(&pck1);
|
|
||||||
clk_register(&pck2);
|
|
||||||
clk_register(&pck3);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct clk_lookup console_clock_lookup;
|
|
||||||
|
|
||||||
void __init at91cap9_set_console_clock(int id)
|
|
||||||
{
|
|
||||||
if (id >= ARRAY_SIZE(usart_clocks_lookups))
|
|
||||||
return;
|
|
||||||
|
|
||||||
console_clock_lookup.con_id = "usart";
|
|
||||||
console_clock_lookup.clk = usart_clocks_lookups[id].clk;
|
|
||||||
clkdev_add(&console_clock_lookup);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
|
||||||
* GPIO
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
|
|
||||||
{
|
|
||||||
.id = AT91CAP9_ID_PIOABCD,
|
|
||||||
.regbase = AT91CAP9_BASE_PIOA,
|
|
||||||
}, {
|
|
||||||
.id = AT91CAP9_ID_PIOABCD,
|
|
||||||
.regbase = AT91CAP9_BASE_PIOB,
|
|
||||||
}, {
|
|
||||||
.id = AT91CAP9_ID_PIOABCD,
|
|
||||||
.regbase = AT91CAP9_BASE_PIOC,
|
|
||||||
}, {
|
|
||||||
.id = AT91CAP9_ID_PIOABCD,
|
|
||||||
.regbase = AT91CAP9_BASE_PIOD,
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
|
||||||
* AT91CAP9 processor initialization
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
static void __init at91cap9_map_io(void)
|
|
||||||
{
|
|
||||||
at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void __init at91cap9_ioremap_registers(void)
|
|
||||||
{
|
|
||||||
at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
|
|
||||||
at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
|
|
||||||
at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
|
|
||||||
at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void __init at91cap9_initialize(void)
|
|
||||||
{
|
|
||||||
arm_pm_restart = at91sam9g45_restart;
|
|
||||||
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
|
|
||||||
|
|
||||||
/* Register GPIO subsystem */
|
|
||||||
at91_gpio_init(at91cap9_gpio, 4);
|
|
||||||
|
|
||||||
/* Remember the silicon revision */
|
|
||||||
if (cpu_is_at91cap9_revB())
|
|
||||||
system_rev = 0xB;
|
|
||||||
else if (cpu_is_at91cap9_revC())
|
|
||||||
system_rev = 0xC;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
|
||||||
* Interrupt initialization
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The default interrupt priority levels (0 = lowest, 7 = highest).
|
|
||||||
*/
|
|
||||||
static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|
||||||
7, /* Advanced Interrupt Controller (FIQ) */
|
|
||||||
7, /* System Peripherals */
|
|
||||||
1, /* Parallel IO Controller A, B, C and D */
|
|
||||||
0, /* MP Block Peripheral 0 */
|
|
||||||
0, /* MP Block Peripheral 1 */
|
|
||||||
0, /* MP Block Peripheral 2 */
|
|
||||||
0, /* MP Block Peripheral 3 */
|
|
||||||
0, /* MP Block Peripheral 4 */
|
|
||||||
5, /* USART 0 */
|
|
||||||
5, /* USART 1 */
|
|
||||||
5, /* USART 2 */
|
|
||||||
0, /* Multimedia Card Interface 0 */
|
|
||||||
0, /* Multimedia Card Interface 1 */
|
|
||||||
3, /* CAN */
|
|
||||||
6, /* Two-Wire Interface */
|
|
||||||
5, /* Serial Peripheral Interface 0 */
|
|
||||||
5, /* Serial Peripheral Interface 1 */
|
|
||||||
4, /* Serial Synchronous Controller 0 */
|
|
||||||
4, /* Serial Synchronous Controller 1 */
|
|
||||||
5, /* AC97 Controller */
|
|
||||||
0, /* Timer Counter 0, 1 and 2 */
|
|
||||||
0, /* Pulse Width Modulation Controller */
|
|
||||||
3, /* Ethernet */
|
|
||||||
0, /* Advanced Encryption Standard, Triple DES*/
|
|
||||||
0, /* Analog-to-Digital Converter */
|
|
||||||
0, /* Image Sensor Interface */
|
|
||||||
3, /* LCD Controller */
|
|
||||||
0, /* DMA Controller */
|
|
||||||
2, /* USB Device Port */
|
|
||||||
2, /* USB Host port */
|
|
||||||
0, /* Advanced Interrupt Controller (IRQ0) */
|
|
||||||
0, /* Advanced Interrupt Controller (IRQ1) */
|
|
||||||
};
|
|
||||||
|
|
||||||
struct at91_init_soc __initdata at91cap9_soc = {
|
|
||||||
.map_io = at91cap9_map_io,
|
|
||||||
.default_irq_priority = at91cap9_default_irq_priority,
|
|
||||||
.ioremap_registers = at91cap9_ioremap_registers,
|
|
||||||
.register_clocks = at91cap9_register_clocks,
|
|
||||||
.init = at91cap9_initialize,
|
|
||||||
};
|
|
File diff suppressed because it is too large
Load diff
|
@ -289,13 +289,22 @@ static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static void at91rm9200_idle(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Disable the processor clock. The processor will be automatically
|
||||||
|
* re-enabled by an interrupt or by a reset.
|
||||||
|
*/
|
||||||
|
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||||
|
}
|
||||||
|
|
||||||
static void at91rm9200_restart(char mode, const char *cmd)
|
static void at91rm9200_restart(char mode, const char *cmd)
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
* Perform a hardware reset with the use of the Watchdog timer.
|
* Perform a hardware reset with the use of the Watchdog timer.
|
||||||
*/
|
*/
|
||||||
at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
|
at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
|
||||||
at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
|
at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
/* --------------------------------------------------------------------
|
||||||
|
@ -310,10 +319,13 @@ static void __init at91rm9200_map_io(void)
|
||||||
|
|
||||||
static void __init at91rm9200_ioremap_registers(void)
|
static void __init at91rm9200_ioremap_registers(void)
|
||||||
{
|
{
|
||||||
|
at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
|
||||||
|
at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __init at91rm9200_initialize(void)
|
static void __init at91rm9200_initialize(void)
|
||||||
{
|
{
|
||||||
|
arm_pm_idle = at91rm9200_idle;
|
||||||
arm_pm_restart = at91rm9200_restart;
|
arm_pm_restart = at91rm9200_restart;
|
||||||
at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
|
at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
|
||||||
| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
|
| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
|
||||||
|
|
|
@ -21,6 +21,7 @@
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91rm9200.h>
|
#include <mach/at91rm9200.h>
|
||||||
#include <mach/at91rm9200_mc.h>
|
#include <mach/at91rm9200_mc.h>
|
||||||
|
#include <mach/at91_ramc.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
|
||||||
|
@ -241,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
|
||||||
data->chipselect = 4; /* can only use EBI ChipSelect 4 */
|
data->chipselect = 4; /* can only use EBI ChipSelect 4 */
|
||||||
|
|
||||||
/* CF takes over CS4, CS5, CS6 */
|
/* CF takes over CS4, CS5, CS6 */
|
||||||
csa = at91_sys_read(AT91_EBI_CSA);
|
csa = at91_ramc_read(0, AT91_EBI_CSA);
|
||||||
at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
|
at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Static memory controller timing adjustments.
|
* Static memory controller timing adjustments.
|
||||||
* REVISIT: these timings are in terms of MCK cycles, so
|
* REVISIT: these timings are in terms of MCK cycles, so
|
||||||
* when MCK changes (cpufreq etc) so must these values...
|
* when MCK changes (cpufreq etc) so must these values...
|
||||||
*/
|
*/
|
||||||
at91_sys_write(AT91_SMC_CSR(4),
|
at91_ramc_write(0, AT91_SMC_CSR(4),
|
||||||
AT91_SMC_ACSS_STD
|
AT91_SMC_ACSS_STD
|
||||||
| AT91_SMC_DBW_16
|
| AT91_SMC_DBW_16
|
||||||
| AT91_SMC_BAT
|
| AT91_SMC_BAT
|
||||||
|
@ -407,11 +408,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
/* enable the address range of CS3 */
|
/* enable the address range of CS3 */
|
||||||
csa = at91_sys_read(AT91_EBI_CSA);
|
csa = at91_ramc_read(0, AT91_EBI_CSA);
|
||||||
at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
|
at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
|
||||||
|
|
||||||
/* set the bus interface characteristics */
|
/* set the bus interface characteristics */
|
||||||
at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
|
at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
|
||||||
| AT91_SMC_NWS_(5)
|
| AT91_SMC_NWS_(5)
|
||||||
| AT91_SMC_TDF_(1)
|
| AT91_SMC_TDF_(1)
|
||||||
| AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
|
| AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
|
||||||
|
@ -1114,7 +1115,6 @@ static inline void configure_usart3_pins(unsigned pins)
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
||||||
struct platform_device *atmel_default_console_device; /* the serial console device */
|
|
||||||
|
|
||||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
||||||
{
|
{
|
||||||
|
|
|
@ -43,9 +43,9 @@ static inline unsigned long read_CRTR(void)
|
||||||
{
|
{
|
||||||
unsigned long x1, x2;
|
unsigned long x1, x2;
|
||||||
|
|
||||||
x1 = at91_sys_read(AT91_ST_CRTR);
|
x1 = at91_st_read(AT91_ST_CRTR);
|
||||||
do {
|
do {
|
||||||
x2 = at91_sys_read(AT91_ST_CRTR);
|
x2 = at91_st_read(AT91_ST_CRTR);
|
||||||
if (x1 == x2)
|
if (x1 == x2)
|
||||||
break;
|
break;
|
||||||
x1 = x2;
|
x1 = x2;
|
||||||
|
@ -58,7 +58,7 @@ static inline unsigned long read_CRTR(void)
|
||||||
*/
|
*/
|
||||||
static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
|
static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
|
||||||
{
|
{
|
||||||
u32 sr = at91_sys_read(AT91_ST_SR) & irqmask;
|
u32 sr = at91_st_read(AT91_ST_SR) & irqmask;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* irqs should be disabled here, but as the irq is shared they are only
|
* irqs should be disabled here, but as the irq is shared they are only
|
||||||
|
@ -110,22 +110,22 @@ static void
|
||||||
clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
|
clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
|
||||||
{
|
{
|
||||||
/* Disable and flush pending timer interrupts */
|
/* Disable and flush pending timer interrupts */
|
||||||
at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
|
at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
|
||||||
(void) at91_sys_read(AT91_ST_SR);
|
at91_st_read(AT91_ST_SR);
|
||||||
|
|
||||||
last_crtr = read_CRTR();
|
last_crtr = read_CRTR();
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
case CLOCK_EVT_MODE_PERIODIC:
|
case CLOCK_EVT_MODE_PERIODIC:
|
||||||
/* PIT for periodic irqs; fixed rate of 1/HZ */
|
/* PIT for periodic irqs; fixed rate of 1/HZ */
|
||||||
irqmask = AT91_ST_PITS;
|
irqmask = AT91_ST_PITS;
|
||||||
at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
|
at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
|
||||||
break;
|
break;
|
||||||
case CLOCK_EVT_MODE_ONESHOT:
|
case CLOCK_EVT_MODE_ONESHOT:
|
||||||
/* ALM for oneshot irqs, set by next_event()
|
/* ALM for oneshot irqs, set by next_event()
|
||||||
* before 32 seconds have passed
|
* before 32 seconds have passed
|
||||||
*/
|
*/
|
||||||
irqmask = AT91_ST_ALMS;
|
irqmask = AT91_ST_ALMS;
|
||||||
at91_sys_write(AT91_ST_RTAR, last_crtr);
|
at91_st_write(AT91_ST_RTAR, last_crtr);
|
||||||
break;
|
break;
|
||||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||||
case CLOCK_EVT_MODE_UNUSED:
|
case CLOCK_EVT_MODE_UNUSED:
|
||||||
|
@ -133,7 +133,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
|
||||||
irqmask = 0;
|
irqmask = 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
at91_sys_write(AT91_ST_IER, irqmask);
|
at91_st_write(AT91_ST_IER, irqmask);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int
|
static int
|
||||||
|
@ -156,12 +156,12 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
|
||||||
alm = read_CRTR();
|
alm = read_CRTR();
|
||||||
|
|
||||||
/* Cancel any pending alarm; flush any pending IRQ */
|
/* Cancel any pending alarm; flush any pending IRQ */
|
||||||
at91_sys_write(AT91_ST_RTAR, alm);
|
at91_st_write(AT91_ST_RTAR, alm);
|
||||||
(void) at91_sys_read(AT91_ST_SR);
|
at91_st_read(AT91_ST_SR);
|
||||||
|
|
||||||
/* Schedule alarm by writing RTAR. */
|
/* Schedule alarm by writing RTAR. */
|
||||||
alm += delta;
|
alm += delta;
|
||||||
at91_sys_write(AT91_ST_RTAR, alm);
|
at91_st_write(AT91_ST_RTAR, alm);
|
||||||
|
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
@ -175,15 +175,24 @@ static struct clock_event_device clkevt = {
|
||||||
.set_mode = clkevt32k_mode,
|
.set_mode = clkevt32k_mode,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
void __iomem *at91_st_base;
|
||||||
|
|
||||||
|
void __init at91rm9200_ioremap_st(u32 addr)
|
||||||
|
{
|
||||||
|
at91_st_base = ioremap(addr, 256);
|
||||||
|
if (!at91_st_base)
|
||||||
|
panic("Impossible to ioremap ST\n");
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* ST (system timer) module supports both clockevents and clocksource.
|
* ST (system timer) module supports both clockevents and clocksource.
|
||||||
*/
|
*/
|
||||||
void __init at91rm9200_timer_init(void)
|
void __init at91rm9200_timer_init(void)
|
||||||
{
|
{
|
||||||
/* Disable all timer interrupts, and clear any pending ones */
|
/* Disable all timer interrupts, and clear any pending ones */
|
||||||
at91_sys_write(AT91_ST_IDR,
|
at91_st_write(AT91_ST_IDR,
|
||||||
AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
|
AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
|
||||||
(void) at91_sys_read(AT91_ST_SR);
|
at91_st_read(AT91_ST_SR);
|
||||||
|
|
||||||
/* Make IRQs happen for the system timer */
|
/* Make IRQs happen for the system timer */
|
||||||
setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
|
setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
|
||||||
|
@ -192,7 +201,7 @@ void __init at91rm9200_timer_init(void)
|
||||||
* directly for the clocksource and all clockevents, after adjusting
|
* directly for the clocksource and all clockevents, after adjusting
|
||||||
* its prescaler from the 1 Hz default.
|
* its prescaler from the 1 Hz default.
|
||||||
*/
|
*/
|
||||||
at91_sys_write(AT91_ST_RTMR, 1);
|
at91_st_write(AT91_ST_RTMR, 1);
|
||||||
|
|
||||||
/* Setup timer clockevent, with minimum of two ticks (important!!) */
|
/* Setup timer clockevent, with minimum of two ticks (important!!) */
|
||||||
clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
|
clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
|
||||||
|
|
|
@ -12,6 +12,7 @@
|
||||||
|
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
|
|
||||||
|
#include <asm/proc-fns.h>
|
||||||
#include <asm/irq.h>
|
#include <asm/irq.h>
|
||||||
#include <asm/mach/arch.h>
|
#include <asm/mach/arch.h>
|
||||||
#include <asm/mach/map.h>
|
#include <asm/mach/map.h>
|
||||||
|
@ -309,27 +310,27 @@ static void __init at91sam9xe_map_io(void)
|
||||||
|
|
||||||
static void __init at91sam9260_map_io(void)
|
static void __init at91sam9260_map_io(void)
|
||||||
{
|
{
|
||||||
if (cpu_is_at91sam9xe()) {
|
if (cpu_is_at91sam9xe())
|
||||||
at91sam9xe_map_io();
|
at91sam9xe_map_io();
|
||||||
} else if (cpu_is_at91sam9g20()) {
|
else if (cpu_is_at91sam9g20())
|
||||||
at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
|
at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
|
||||||
at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
|
else
|
||||||
} else {
|
at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
|
||||||
at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
|
|
||||||
at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __init at91sam9260_ioremap_registers(void)
|
static void __init at91sam9260_ioremap_registers(void)
|
||||||
{
|
{
|
||||||
at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
|
at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
|
||||||
at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
|
at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
|
||||||
|
at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
|
||||||
at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
|
at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
|
||||||
at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
|
at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
|
||||||
|
at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __init at91sam9260_initialize(void)
|
static void __init at91sam9260_initialize(void)
|
||||||
{
|
{
|
||||||
|
arm_pm_idle = at91sam9_idle;
|
||||||
arm_pm_restart = at91sam9_alt_restart;
|
arm_pm_restart = at91sam9_alt_restart;
|
||||||
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
|
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
|
||||||
| (1 << AT91SAM9260_ID_IRQ2);
|
| (1 << AT91SAM9260_ID_IRQ2);
|
||||||
|
|
|
@ -21,6 +21,7 @@
|
||||||
#include <mach/cpu.h>
|
#include <mach/cpu.h>
|
||||||
#include <mach/at91sam9260.h>
|
#include <mach/at91sam9260.h>
|
||||||
#include <mach/at91sam9260_matrix.h>
|
#include <mach/at91sam9260_matrix.h>
|
||||||
|
#include <mach/at91_matrix.h>
|
||||||
#include <mach/at91sam9_smc.h>
|
#include <mach/at91sam9_smc.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
|
||||||
if (!data)
|
if (!data)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
|
||||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
|
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
|
||||||
|
|
||||||
/* enable pin */
|
/* enable pin */
|
||||||
if (gpio_is_valid(data->enable_pin))
|
if (gpio_is_valid(data->enable_pin))
|
||||||
|
@ -717,18 +718,42 @@ static struct resource rtt_resources[] = {
|
||||||
.start = AT91SAM9260_BASE_RTT,
|
.start = AT91SAM9260_BASE_RTT,
|
||||||
.end = AT91SAM9260_BASE_RTT + SZ_16 - 1,
|
.end = AT91SAM9260_BASE_RTT + SZ_16 - 1,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
}
|
}, {
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device at91sam9260_rtt_device = {
|
static struct platform_device at91sam9260_rtt_device = {
|
||||||
.name = "at91_rtt",
|
.name = "at91_rtt",
|
||||||
.id = 0,
|
.id = 0,
|
||||||
.resource = rtt_resources,
|
.resource = rtt_resources,
|
||||||
.num_resources = ARRAY_SIZE(rtt_resources),
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
|
||||||
|
static void __init at91_add_device_rtt_rtc(void)
|
||||||
|
{
|
||||||
|
at91sam9260_rtt_device.name = "rtc-at91sam9";
|
||||||
|
/*
|
||||||
|
* The second resource is needed:
|
||||||
|
* GPBR will serve as the storage for RTC time offset
|
||||||
|
*/
|
||||||
|
at91sam9260_rtt_device.num_resources = 2;
|
||||||
|
rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
|
||||||
|
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||||
|
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
static void __init at91_add_device_rtt_rtc(void)
|
||||||
|
{
|
||||||
|
/* Only one resource is needed: RTT not used as RTC */
|
||||||
|
at91sam9260_rtt_device.num_resources = 1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
static void __init at91_add_device_rtt(void)
|
static void __init at91_add_device_rtt(void)
|
||||||
{
|
{
|
||||||
|
at91_add_device_rtt_rtc();
|
||||||
platform_device_register(&at91sam9260_rtt_device);
|
platform_device_register(&at91sam9260_rtt_device);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1139,7 +1164,6 @@ static inline void configure_usart5_pins(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
||||||
struct platform_device *atmel_default_console_device; /* the serial console device */
|
|
||||||
|
|
||||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
||||||
{
|
{
|
||||||
|
@ -1265,7 +1289,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
|
||||||
if (!data)
|
if (!data)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
|
||||||
|
|
||||||
switch (data->chipselect) {
|
switch (data->chipselect) {
|
||||||
case 4:
|
case 4:
|
||||||
|
@ -1288,7 +1312,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
at91_sys_write(AT91_MATRIX_EBICSA, csa);
|
at91_matrix_write(AT91_MATRIX_EBICSA, csa);
|
||||||
|
|
||||||
if (gpio_is_valid(data->rst_pin)) {
|
if (gpio_is_valid(data->rst_pin)) {
|
||||||
at91_set_multi_drive(data->rst_pin, 0);
|
at91_set_multi_drive(data->rst_pin, 0);
|
||||||
|
|
|
@ -12,6 +12,7 @@
|
||||||
|
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
|
|
||||||
|
#include <asm/proc-fns.h>
|
||||||
#include <asm/irq.h>
|
#include <asm/irq.h>
|
||||||
#include <asm/mach/arch.h>
|
#include <asm/mach/arch.h>
|
||||||
#include <asm/mach/map.h>
|
#include <asm/mach/map.h>
|
||||||
|
@ -282,12 +283,15 @@ static void __init at91sam9261_ioremap_registers(void)
|
||||||
{
|
{
|
||||||
at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
|
at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
|
||||||
at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
|
at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
|
||||||
|
at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
|
||||||
at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
|
at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
|
||||||
at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
|
at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
|
||||||
|
at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __init at91sam9261_initialize(void)
|
static void __init at91sam9261_initialize(void)
|
||||||
{
|
{
|
||||||
|
arm_pm_idle = at91sam9_idle;
|
||||||
arm_pm_restart = at91sam9_alt_restart;
|
arm_pm_restart = at91sam9_alt_restart;
|
||||||
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
|
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
|
||||||
| (1 << AT91SAM9261_ID_IRQ2);
|
| (1 << AT91SAM9261_ID_IRQ2);
|
||||||
|
|
|
@ -24,6 +24,7 @@
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91sam9261.h>
|
#include <mach/at91sam9261.h>
|
||||||
#include <mach/at91sam9261_matrix.h>
|
#include <mach/at91sam9261_matrix.h>
|
||||||
|
#include <mach/at91_matrix.h>
|
||||||
#include <mach/at91sam9_smc.h>
|
#include <mach/at91sam9_smc.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
|
||||||
if (!data)
|
if (!data)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
|
||||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
|
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
|
||||||
|
|
||||||
/* enable pin */
|
/* enable pin */
|
||||||
if (gpio_is_valid(data->enable_pin))
|
if (gpio_is_valid(data->enable_pin))
|
||||||
|
@ -603,6 +604,8 @@ static struct resource rtt_resources[] = {
|
||||||
.start = AT91SAM9261_BASE_RTT,
|
.start = AT91SAM9261_BASE_RTT,
|
||||||
.end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
|
.end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -610,11 +613,32 @@ static struct platform_device at91sam9261_rtt_device = {
|
||||||
.name = "at91_rtt",
|
.name = "at91_rtt",
|
||||||
.id = 0,
|
.id = 0,
|
||||||
.resource = rtt_resources,
|
.resource = rtt_resources,
|
||||||
.num_resources = ARRAY_SIZE(rtt_resources),
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
|
||||||
|
static void __init at91_add_device_rtt_rtc(void)
|
||||||
|
{
|
||||||
|
at91sam9261_rtt_device.name = "rtc-at91sam9";
|
||||||
|
/*
|
||||||
|
* The second resource is needed:
|
||||||
|
* GPBR will serve as the storage for RTC time offset
|
||||||
|
*/
|
||||||
|
at91sam9261_rtt_device.num_resources = 2;
|
||||||
|
rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
|
||||||
|
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||||
|
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
static void __init at91_add_device_rtt_rtc(void)
|
||||||
|
{
|
||||||
|
/* Only one resource is needed: RTT not used as RTC */
|
||||||
|
at91sam9261_rtt_device.num_resources = 1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
static void __init at91_add_device_rtt(void)
|
static void __init at91_add_device_rtt(void)
|
||||||
{
|
{
|
||||||
|
at91_add_device_rtt_rtc();
|
||||||
platform_device_register(&at91sam9261_rtt_device);
|
platform_device_register(&at91sam9261_rtt_device);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -991,7 +1015,6 @@ static inline void configure_usart2_pins(unsigned pins)
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
||||||
struct platform_device *atmel_default_console_device; /* the serial console device */
|
|
||||||
|
|
||||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
||||||
{
|
{
|
||||||
|
|
|
@ -12,6 +12,7 @@
|
||||||
|
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
|
|
||||||
|
#include <asm/proc-fns.h>
|
||||||
#include <asm/irq.h>
|
#include <asm/irq.h>
|
||||||
#include <asm/mach/arch.h>
|
#include <asm/mach/arch.h>
|
||||||
#include <asm/mach/map.h>
|
#include <asm/mach/map.h>
|
||||||
|
@ -302,13 +303,17 @@ static void __init at91sam9263_ioremap_registers(void)
|
||||||
{
|
{
|
||||||
at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
|
at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
|
||||||
at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
|
at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
|
||||||
|
at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
|
||||||
|
at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
|
||||||
at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
|
at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
|
||||||
at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
|
at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
|
||||||
at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
|
at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
|
||||||
|
at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __init at91sam9263_initialize(void)
|
static void __init at91sam9263_initialize(void)
|
||||||
{
|
{
|
||||||
|
arm_pm_idle = at91sam9_idle;
|
||||||
arm_pm_restart = at91sam9_alt_restart;
|
arm_pm_restart = at91sam9_alt_restart;
|
||||||
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
|
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
|
||||||
|
|
||||||
|
|
|
@ -23,6 +23,7 @@
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91sam9263.h>
|
#include <mach/at91sam9263.h>
|
||||||
#include <mach/at91sam9263_matrix.h>
|
#include <mach/at91sam9263_matrix.h>
|
||||||
|
#include <mach/at91_matrix.h>
|
||||||
#include <mach/at91sam9_smc.h>
|
#include <mach/at91sam9_smc.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
|
||||||
* we assume SMC timings are configured by board code,
|
* we assume SMC timings are configured by board code,
|
||||||
* except True IDE where timings are controlled by driver
|
* except True IDE where timings are controlled by driver
|
||||||
*/
|
*/
|
||||||
ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
|
ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
|
||||||
switch (data->chipselect) {
|
switch (data->chipselect) {
|
||||||
case 4:
|
case 4:
|
||||||
at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
|
at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
|
||||||
|
@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
|
||||||
data->chipselect);
|
data->chipselect);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
|
at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
|
||||||
|
|
||||||
if (gpio_is_valid(data->det_pin)) {
|
if (gpio_is_valid(data->det_pin)) {
|
||||||
at91_set_gpio_input(data->det_pin, 1);
|
at91_set_gpio_input(data->det_pin, 1);
|
||||||
|
@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
|
||||||
if (!data)
|
if (!data)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
|
csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
|
||||||
at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
|
at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
|
||||||
|
|
||||||
/* enable pin */
|
/* enable pin */
|
||||||
if (gpio_is_valid(data->enable_pin))
|
if (gpio_is_valid(data->enable_pin))
|
||||||
|
@ -891,7 +892,8 @@ static struct platform_device at91sam9263_isi_device = {
|
||||||
.num_resources = ARRAY_SIZE(isi_resources),
|
.num_resources = ARRAY_SIZE(isi_resources),
|
||||||
};
|
};
|
||||||
|
|
||||||
void __init at91_add_device_isi(void)
|
void __init at91_add_device_isi(struct isi_platform_data *data,
|
||||||
|
bool use_pck_as_mck)
|
||||||
{
|
{
|
||||||
at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
|
at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
|
||||||
at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
|
at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
|
||||||
|
@ -904,14 +906,20 @@ void __init at91_add_device_isi(void)
|
||||||
at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
|
at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
|
||||||
at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
|
at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
|
||||||
at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
|
at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
|
||||||
at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
|
|
||||||
at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
|
at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
|
||||||
at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
|
at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
|
||||||
at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
|
at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
|
||||||
at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
|
at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
|
||||||
|
|
||||||
|
if (use_pck_as_mck) {
|
||||||
|
at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
|
||||||
|
|
||||||
|
/* TODO: register the PCK for ISI_MCK and set its parent */
|
||||||
|
}
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
void __init at91_add_device_isi(void) {}
|
void __init at91_add_device_isi(struct isi_platform_data *data,
|
||||||
|
bool use_pck_as_mck) {}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
@ -959,6 +967,8 @@ static struct resource rtt0_resources[] = {
|
||||||
.start = AT91SAM9263_BASE_RTT0,
|
.start = AT91SAM9263_BASE_RTT0,
|
||||||
.end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
|
.end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -966,7 +976,6 @@ static struct platform_device at91sam9263_rtt0_device = {
|
||||||
.name = "at91_rtt",
|
.name = "at91_rtt",
|
||||||
.id = 0,
|
.id = 0,
|
||||||
.resource = rtt0_resources,
|
.resource = rtt0_resources,
|
||||||
.num_resources = ARRAY_SIZE(rtt0_resources),
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct resource rtt1_resources[] = {
|
static struct resource rtt1_resources[] = {
|
||||||
|
@ -974,6 +983,8 @@ static struct resource rtt1_resources[] = {
|
||||||
.start = AT91SAM9263_BASE_RTT1,
|
.start = AT91SAM9263_BASE_RTT1,
|
||||||
.end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
|
.end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -981,11 +992,53 @@ static struct platform_device at91sam9263_rtt1_device = {
|
||||||
.name = "at91_rtt",
|
.name = "at91_rtt",
|
||||||
.id = 1,
|
.id = 1,
|
||||||
.resource = rtt1_resources,
|
.resource = rtt1_resources,
|
||||||
.num_resources = ARRAY_SIZE(rtt1_resources),
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
|
||||||
|
static void __init at91_add_device_rtt_rtc(void)
|
||||||
|
{
|
||||||
|
struct platform_device *pdev;
|
||||||
|
struct resource *r;
|
||||||
|
|
||||||
|
switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
|
||||||
|
case 0:
|
||||||
|
/*
|
||||||
|
* The second resource is needed only for the chosen RTT:
|
||||||
|
* GPBR will serve as the storage for RTC time offset
|
||||||
|
*/
|
||||||
|
at91sam9263_rtt0_device.num_resources = 2;
|
||||||
|
at91sam9263_rtt1_device.num_resources = 1;
|
||||||
|
pdev = &at91sam9263_rtt0_device;
|
||||||
|
r = rtt0_resources;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
at91sam9263_rtt0_device.num_resources = 1;
|
||||||
|
at91sam9263_rtt1_device.num_resources = 2;
|
||||||
|
pdev = &at91sam9263_rtt1_device;
|
||||||
|
r = rtt1_resources;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
pr_err("at91sam9263: only supports 2 RTT (%d)\n",
|
||||||
|
CONFIG_RTC_DRV_AT91SAM9_RTT);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
pdev->name = "rtc-at91sam9";
|
||||||
|
r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||||
|
r[1].end = r[1].start + 3;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
static void __init at91_add_device_rtt_rtc(void)
|
||||||
|
{
|
||||||
|
/* Only one resource is needed: RTT not used as RTC */
|
||||||
|
at91sam9263_rtt0_device.num_resources = 1;
|
||||||
|
at91sam9263_rtt1_device.num_resources = 1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
static void __init at91_add_device_rtt(void)
|
static void __init at91_add_device_rtt(void)
|
||||||
{
|
{
|
||||||
|
at91_add_device_rtt_rtc();
|
||||||
platform_device_register(&at91sam9263_rtt0_device);
|
platform_device_register(&at91sam9263_rtt0_device);
|
||||||
platform_device_register(&at91sam9263_rtt1_device);
|
platform_device_register(&at91sam9263_rtt1_device);
|
||||||
}
|
}
|
||||||
|
@ -1371,7 +1424,6 @@ static inline void configure_usart2_pins(unsigned pins)
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
||||||
struct platform_device *atmel_default_console_device; /* the serial console device */
|
|
||||||
|
|
||||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
||||||
{
|
{
|
||||||
|
|
|
@ -15,16 +15,17 @@
|
||||||
|
|
||||||
#include <linux/linkage.h>
|
#include <linux/linkage.h>
|
||||||
#include <mach/hardware.h>
|
#include <mach/hardware.h>
|
||||||
#include <mach/at91sam9_sdramc.h>
|
#include <mach/at91_ramc.h>
|
||||||
#include <mach/at91_rstc.h>
|
#include <mach/at91_rstc.h>
|
||||||
|
|
||||||
.arm
|
.arm
|
||||||
|
|
||||||
.globl at91sam9_alt_restart
|
.globl at91sam9_alt_restart
|
||||||
|
|
||||||
at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
|
at91sam9_alt_restart: ldr r0, =at91_ramc_base @ preload constants
|
||||||
ldr r1, =at91_rstc_base
|
ldr r0, [r0]
|
||||||
ldr r1, [r1]
|
ldr r4, =at91_rstc_base
|
||||||
|
ldr r1, [r4]
|
||||||
|
|
||||||
mov r2, #1
|
mov r2, #1
|
||||||
mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
|
mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
|
||||||
|
@ -37,6 +38,3 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
|
||||||
str r4, [r1, #AT91_RSTC_CR] @ reset processor
|
str r4, [r1, #AT91_RSTC_CR] @ reset processor
|
||||||
|
|
||||||
b .
|
b .
|
||||||
|
|
||||||
.at91_va_base_sdramc:
|
|
||||||
.word AT91_VA_BASE_SYS + AT91_SDRAMC0
|
|
||||||
|
|
|
@ -331,12 +331,16 @@ static void __init at91sam9g45_ioremap_registers(void)
|
||||||
{
|
{
|
||||||
at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
|
at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
|
||||||
at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
|
at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
|
||||||
|
at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
|
||||||
|
at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
|
||||||
at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
|
at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
|
||||||
at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
|
at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
|
||||||
|
at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __init at91sam9g45_initialize(void)
|
static void __init at91sam9g45_initialize(void)
|
||||||
{
|
{
|
||||||
|
arm_pm_idle = at91sam9_idle;
|
||||||
arm_pm_restart = at91sam9g45_restart;
|
arm_pm_restart = at91sam9g45_restart;
|
||||||
at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
|
at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
|
||||||
|
|
||||||
|
|
|
@ -14,6 +14,7 @@
|
||||||
|
|
||||||
#include <linux/dma-mapping.h>
|
#include <linux/dma-mapping.h>
|
||||||
#include <linux/gpio.h>
|
#include <linux/gpio.h>
|
||||||
|
#include <linux/clk.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/i2c-gpio.h>
|
#include <linux/i2c-gpio.h>
|
||||||
#include <linux/atmel-mci.h>
|
#include <linux/atmel-mci.h>
|
||||||
|
@ -24,11 +25,15 @@
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91sam9g45.h>
|
#include <mach/at91sam9g45.h>
|
||||||
#include <mach/at91sam9g45_matrix.h>
|
#include <mach/at91sam9g45_matrix.h>
|
||||||
|
#include <mach/at91_matrix.h>
|
||||||
#include <mach/at91sam9_smc.h>
|
#include <mach/at91sam9_smc.h>
|
||||||
#include <mach/at_hdmac.h>
|
#include <mach/at_hdmac.h>
|
||||||
#include <mach/atmel-mci.h>
|
#include <mach/atmel-mci.h>
|
||||||
|
|
||||||
|
#include <media/atmel-isi.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
#include "clock.h"
|
||||||
|
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
/* --------------------------------------------------------------------
|
||||||
|
@ -38,10 +43,6 @@
|
||||||
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
|
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
|
||||||
static u64 hdmac_dmamask = DMA_BIT_MASK(32);
|
static u64 hdmac_dmamask = DMA_BIT_MASK(32);
|
||||||
|
|
||||||
static struct at_dma_platform_data atdma_pdata = {
|
|
||||||
.nr_channels = 8,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct resource hdmac_resources[] = {
|
static struct resource hdmac_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.start = AT91SAM9G45_BASE_DMA,
|
.start = AT91SAM9G45_BASE_DMA,
|
||||||
|
@ -56,12 +57,11 @@ static struct resource hdmac_resources[] = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device at_hdmac_device = {
|
static struct platform_device at_hdmac_device = {
|
||||||
.name = "at_hdmac",
|
.name = "at91sam9g45_dma",
|
||||||
.id = -1,
|
.id = -1,
|
||||||
.dev = {
|
.dev = {
|
||||||
.dma_mask = &hdmac_dmamask,
|
.dma_mask = &hdmac_dmamask,
|
||||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||||
.platform_data = &atdma_pdata,
|
|
||||||
},
|
},
|
||||||
.resource = hdmac_resources,
|
.resource = hdmac_resources,
|
||||||
.num_resources = ARRAY_SIZE(hdmac_resources),
|
.num_resources = ARRAY_SIZE(hdmac_resources),
|
||||||
|
@ -69,9 +69,15 @@ static struct platform_device at_hdmac_device = {
|
||||||
|
|
||||||
void __init at91_add_device_hdmac(void)
|
void __init at91_add_device_hdmac(void)
|
||||||
{
|
{
|
||||||
dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
|
#if defined(CONFIG_OF)
|
||||||
dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
|
struct device_node *of_node =
|
||||||
platform_device_register(&at_hdmac_device);
|
of_find_node_by_name(NULL, "dma-controller");
|
||||||
|
|
||||||
|
if (of_node)
|
||||||
|
of_node_put(of_node);
|
||||||
|
else
|
||||||
|
#endif
|
||||||
|
platform_device_register(&at_hdmac_device);
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
void __init at91_add_device_hdmac(void) {}
|
void __init at91_add_device_hdmac(void) {}
|
||||||
|
@ -552,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
|
||||||
if (!data)
|
if (!data)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
|
||||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
|
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
|
||||||
|
|
||||||
/* enable pin */
|
/* enable pin */
|
||||||
if (gpio_is_valid(data->enable_pin))
|
if (gpio_is_valid(data->enable_pin))
|
||||||
|
@ -869,6 +875,96 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
|
||||||
void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
|
void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Image Sensor Interface
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
|
||||||
|
static u64 isi_dmamask = DMA_BIT_MASK(32);
|
||||||
|
static struct isi_platform_data isi_data;
|
||||||
|
|
||||||
|
struct resource isi_resources[] = {
|
||||||
|
[0] = {
|
||||||
|
.start = AT91SAM9G45_BASE_ISI,
|
||||||
|
.end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
},
|
||||||
|
[1] = {
|
||||||
|
.start = AT91SAM9G45_ID_ISI,
|
||||||
|
.end = AT91SAM9G45_ID_ISI,
|
||||||
|
.flags = IORESOURCE_IRQ,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device at91sam9g45_isi_device = {
|
||||||
|
.name = "atmel_isi",
|
||||||
|
.id = 0,
|
||||||
|
.dev = {
|
||||||
|
.dma_mask = &isi_dmamask,
|
||||||
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||||
|
.platform_data = &isi_data,
|
||||||
|
},
|
||||||
|
.resource = isi_resources,
|
||||||
|
.num_resources = ARRAY_SIZE(isi_resources),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct clk_lookup isi_mck_lookups[] = {
|
||||||
|
CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
|
||||||
|
};
|
||||||
|
|
||||||
|
void __init at91_add_device_isi(struct isi_platform_data *data,
|
||||||
|
bool use_pck_as_mck)
|
||||||
|
{
|
||||||
|
struct clk *pck;
|
||||||
|
struct clk *parent;
|
||||||
|
|
||||||
|
if (!data)
|
||||||
|
return;
|
||||||
|
isi_data = *data;
|
||||||
|
|
||||||
|
at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
|
||||||
|
at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
|
||||||
|
at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
|
||||||
|
at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
|
||||||
|
at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
|
||||||
|
at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
|
||||||
|
at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
|
||||||
|
|
||||||
|
platform_device_register(&at91sam9g45_isi_device);
|
||||||
|
|
||||||
|
if (use_pck_as_mck) {
|
||||||
|
at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
|
||||||
|
|
||||||
|
pck = clk_get(NULL, "pck1");
|
||||||
|
parent = clk_get(NULL, "plla");
|
||||||
|
|
||||||
|
BUG_ON(IS_ERR(pck) || IS_ERR(parent));
|
||||||
|
|
||||||
|
if (clk_set_parent(pck, parent)) {
|
||||||
|
pr_err("Failed to set PCK's parent\n");
|
||||||
|
} else {
|
||||||
|
/* Register PCK as ISI_MCK */
|
||||||
|
isi_mck_lookups[0].clk = pck;
|
||||||
|
clkdev_add_table(isi_mck_lookups,
|
||||||
|
ARRAY_SIZE(isi_mck_lookups));
|
||||||
|
}
|
||||||
|
|
||||||
|
clk_put(pck);
|
||||||
|
clk_put(parent);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
void __init at91_add_device_isi(struct isi_platform_data *data,
|
||||||
|
bool use_pck_as_mck) {}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
/* --------------------------------------------------------------------
|
||||||
* LCD Controller
|
* LCD Controller
|
||||||
|
@ -1098,6 +1194,8 @@ static struct resource rtt_resources[] = {
|
||||||
.start = AT91SAM9G45_BASE_RTT,
|
.start = AT91SAM9G45_BASE_RTT,
|
||||||
.end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
|
.end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -1105,11 +1203,32 @@ static struct platform_device at91sam9g45_rtt_device = {
|
||||||
.name = "at91_rtt",
|
.name = "at91_rtt",
|
||||||
.id = 0,
|
.id = 0,
|
||||||
.resource = rtt_resources,
|
.resource = rtt_resources,
|
||||||
.num_resources = ARRAY_SIZE(rtt_resources),
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
|
||||||
|
static void __init at91_add_device_rtt_rtc(void)
|
||||||
|
{
|
||||||
|
at91sam9g45_rtt_device.name = "rtc-at91sam9";
|
||||||
|
/*
|
||||||
|
* The second resource is needed:
|
||||||
|
* GPBR will serve as the storage for RTC time offset
|
||||||
|
*/
|
||||||
|
at91sam9g45_rtt_device.num_resources = 2;
|
||||||
|
rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
|
||||||
|
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||||
|
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
static void __init at91_add_device_rtt_rtc(void)
|
||||||
|
{
|
||||||
|
/* Only one resource is needed: RTT not used as RTC */
|
||||||
|
at91sam9g45_rtt_device.num_resources = 1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
static void __init at91_add_device_rtt(void)
|
static void __init at91_add_device_rtt(void)
|
||||||
{
|
{
|
||||||
|
at91_add_device_rtt_rtc();
|
||||||
platform_device_register(&at91sam9g45_rtt_device);
|
platform_device_register(&at91sam9g45_rtt_device);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1564,7 +1683,6 @@ static inline void configure_usart3_pins(unsigned pins)
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
||||||
struct platform_device *atmel_default_console_device; /* the serial console device */
|
|
||||||
|
|
||||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
||||||
{
|
{
|
||||||
|
|
|
@ -12,7 +12,7 @@
|
||||||
|
|
||||||
#include <linux/linkage.h>
|
#include <linux/linkage.h>
|
||||||
#include <mach/hardware.h>
|
#include <mach/hardware.h>
|
||||||
#include <mach/at91sam9_ddrsdr.h>
|
#include <mach/at91_ramc.h>
|
||||||
#include <mach/at91_rstc.h>
|
#include <mach/at91_rstc.h>
|
||||||
|
|
||||||
.arm
|
.arm
|
||||||
|
@ -20,9 +20,10 @@
|
||||||
.globl at91sam9g45_restart
|
.globl at91sam9g45_restart
|
||||||
|
|
||||||
at91sam9g45_restart:
|
at91sam9g45_restart:
|
||||||
ldr r0, .at91_va_base_sdramc0 @ preload constants
|
ldr r5, =at91_ramc_base @ preload constants
|
||||||
ldr r1, =at91_rstc_base
|
ldr r0, [r5]
|
||||||
ldr r1, [r1]
|
ldr r4, =at91_rstc_base
|
||||||
|
ldr r1, [r4]
|
||||||
|
|
||||||
mov r2, #1
|
mov r2, #1
|
||||||
mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
|
mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
|
||||||
|
@ -35,6 +36,3 @@ at91sam9g45_restart:
|
||||||
str r4, [r1, #AT91_RSTC_CR] @ reset processor
|
str r4, [r1, #AT91_RSTC_CR] @ reset processor
|
||||||
|
|
||||||
b .
|
b .
|
||||||
|
|
||||||
.at91_va_base_sdramc0:
|
|
||||||
.word AT91_VA_BASE_SYS + AT91_DDRSDRC0
|
|
||||||
|
|
|
@ -11,6 +11,7 @@
|
||||||
|
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
|
|
||||||
|
#include <asm/proc-fns.h>
|
||||||
#include <asm/irq.h>
|
#include <asm/irq.h>
|
||||||
#include <asm/mach/arch.h>
|
#include <asm/mach/arch.h>
|
||||||
#include <asm/mach/map.h>
|
#include <asm/mach/map.h>
|
||||||
|
@ -287,12 +288,15 @@ static void __init at91sam9rl_ioremap_registers(void)
|
||||||
{
|
{
|
||||||
at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
|
at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
|
||||||
at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
|
at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
|
||||||
|
at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
|
||||||
at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
|
at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
|
||||||
at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
|
at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
|
||||||
|
at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __init at91sam9rl_initialize(void)
|
static void __init at91sam9rl_initialize(void)
|
||||||
{
|
{
|
||||||
|
arm_pm_idle = at91sam9_idle;
|
||||||
arm_pm_restart = at91sam9_alt_restart;
|
arm_pm_restart = at91sam9_alt_restart;
|
||||||
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
|
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
|
||||||
|
|
||||||
|
|
|
@ -20,6 +20,7 @@
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91sam9rl.h>
|
#include <mach/at91sam9rl.h>
|
||||||
#include <mach/at91sam9rl_matrix.h>
|
#include <mach/at91sam9rl_matrix.h>
|
||||||
|
#include <mach/at91_matrix.h>
|
||||||
#include <mach/at91sam9_smc.h>
|
#include <mach/at91sam9_smc.h>
|
||||||
#include <mach/at_hdmac.h>
|
#include <mach/at_hdmac.h>
|
||||||
|
|
||||||
|
@ -33,10 +34,6 @@
|
||||||
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
|
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
|
||||||
static u64 hdmac_dmamask = DMA_BIT_MASK(32);
|
static u64 hdmac_dmamask = DMA_BIT_MASK(32);
|
||||||
|
|
||||||
static struct at_dma_platform_data atdma_pdata = {
|
|
||||||
.nr_channels = 2,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct resource hdmac_resources[] = {
|
static struct resource hdmac_resources[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
.start = AT91SAM9RL_BASE_DMA,
|
.start = AT91SAM9RL_BASE_DMA,
|
||||||
|
@ -51,12 +48,11 @@ static struct resource hdmac_resources[] = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device at_hdmac_device = {
|
static struct platform_device at_hdmac_device = {
|
||||||
.name = "at_hdmac",
|
.name = "at91sam9rl_dma",
|
||||||
.id = -1,
|
.id = -1,
|
||||||
.dev = {
|
.dev = {
|
||||||
.dma_mask = &hdmac_dmamask,
|
.dma_mask = &hdmac_dmamask,
|
||||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||||
.platform_data = &atdma_pdata,
|
|
||||||
},
|
},
|
||||||
.resource = hdmac_resources,
|
.resource = hdmac_resources,
|
||||||
.num_resources = ARRAY_SIZE(hdmac_resources),
|
.num_resources = ARRAY_SIZE(hdmac_resources),
|
||||||
|
@ -64,7 +60,6 @@ static struct platform_device at_hdmac_device = {
|
||||||
|
|
||||||
void __init at91_add_device_hdmac(void)
|
void __init at91_add_device_hdmac(void)
|
||||||
{
|
{
|
||||||
dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
|
|
||||||
platform_device_register(&at_hdmac_device);
|
platform_device_register(&at_hdmac_device);
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
|
@ -271,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
|
||||||
if (!data)
|
if (!data)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
|
||||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
|
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
|
||||||
|
|
||||||
/* enable pin */
|
/* enable pin */
|
||||||
if (gpio_is_valid(data->enable_pin))
|
if (gpio_is_valid(data->enable_pin))
|
||||||
|
@ -688,6 +683,8 @@ static struct resource rtt_resources[] = {
|
||||||
.start = AT91SAM9RL_BASE_RTT,
|
.start = AT91SAM9RL_BASE_RTT,
|
||||||
.end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
|
.end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
|
||||||
.flags = IORESOURCE_MEM,
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -695,11 +692,32 @@ static struct platform_device at91sam9rl_rtt_device = {
|
||||||
.name = "at91_rtt",
|
.name = "at91_rtt",
|
||||||
.id = 0,
|
.id = 0,
|
||||||
.resource = rtt_resources,
|
.resource = rtt_resources,
|
||||||
.num_resources = ARRAY_SIZE(rtt_resources),
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
|
||||||
|
static void __init at91_add_device_rtt_rtc(void)
|
||||||
|
{
|
||||||
|
at91sam9rl_rtt_device.name = "rtc-at91sam9";
|
||||||
|
/*
|
||||||
|
* The second resource is needed:
|
||||||
|
* GPBR will serve as the storage for RTC time offset
|
||||||
|
*/
|
||||||
|
at91sam9rl_rtt_device.num_resources = 2;
|
||||||
|
rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
|
||||||
|
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||||
|
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
static void __init at91_add_device_rtt_rtc(void)
|
||||||
|
{
|
||||||
|
/* Only one resource is needed: RTT not used as RTC */
|
||||||
|
at91sam9rl_rtt_device.num_resources = 1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
static void __init at91_add_device_rtt(void)
|
static void __init at91_add_device_rtt(void)
|
||||||
{
|
{
|
||||||
|
at91_add_device_rtt_rtc();
|
||||||
platform_device_register(&at91sam9rl_rtt_device);
|
platform_device_register(&at91sam9rl_rtt_device);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1134,7 +1152,6 @@ static inline void configure_usart3_pins(unsigned pins)
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
||||||
struct platform_device *atmel_default_console_device; /* the serial console device */
|
|
||||||
|
|
||||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
||||||
{
|
{
|
||||||
|
|
370
arch/arm/mach-at91/at91sam9x5.c
Normal file
370
arch/arm/mach-at91/at91sam9x5.c
Normal file
|
@ -0,0 +1,370 @@
|
||||||
|
/*
|
||||||
|
* Chip-specific setup code for the AT91SAM9x5 family
|
||||||
|
*
|
||||||
|
* Copyright (C) 2010-2012 Atmel Corporation.
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/dma-mapping.h>
|
||||||
|
|
||||||
|
#include <asm/irq.h>
|
||||||
|
#include <asm/mach/arch.h>
|
||||||
|
#include <asm/mach/map.h>
|
||||||
|
#include <mach/at91sam9x5.h>
|
||||||
|
#include <mach/at91_pmc.h>
|
||||||
|
#include <mach/cpu.h>
|
||||||
|
#include <mach/board.h>
|
||||||
|
|
||||||
|
#include "soc.h"
|
||||||
|
#include "generic.h"
|
||||||
|
#include "clock.h"
|
||||||
|
#include "sam9_smc.h"
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Clocks
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The peripheral clocks.
|
||||||
|
*/
|
||||||
|
static struct clk pioAB_clk = {
|
||||||
|
.name = "pioAB_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk pioCD_clk = {
|
||||||
|
.name = "pioCD_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk smd_clk = {
|
||||||
|
.name = "smd_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_SMD,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk usart0_clk = {
|
||||||
|
.name = "usart0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_USART0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk usart1_clk = {
|
||||||
|
.name = "usart1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_USART1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk usart2_clk = {
|
||||||
|
.name = "usart2_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_USART2,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* USART3 clock - Only for sam9g25/sam9x25 */
|
||||||
|
static struct clk usart3_clk = {
|
||||||
|
.name = "usart3_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_USART3,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk twi0_clk = {
|
||||||
|
.name = "twi0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk twi1_clk = {
|
||||||
|
.name = "twi1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk twi2_clk = {
|
||||||
|
.name = "twi2_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk mmc0_clk = {
|
||||||
|
.name = "mci0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk spi0_clk = {
|
||||||
|
.name = "spi0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk spi1_clk = {
|
||||||
|
.name = "spi1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk uart0_clk = {
|
||||||
|
.name = "uart0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_UART0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk uart1_clk = {
|
||||||
|
.name = "uart1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_UART1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk tcb0_clk = {
|
||||||
|
.name = "tcb0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_TCB,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk pwm_clk = {
|
||||||
|
.name = "pwm_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_PWM,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk adc_clk = {
|
||||||
|
.name = "adc_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_ADC,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk dma0_clk = {
|
||||||
|
.name = "dma0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk dma1_clk = {
|
||||||
|
.name = "dma1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk uhphs_clk = {
|
||||||
|
.name = "uhphs_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk udphs_clk = {
|
||||||
|
.name = "udphs_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
|
||||||
|
static struct clk macb0_clk = {
|
||||||
|
.name = "pclk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
|
||||||
|
static struct clk lcdc_clk = {
|
||||||
|
.name = "lcdc_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* isi clock - Only for sam9g25 */
|
||||||
|
static struct clk isi_clk = {
|
||||||
|
.name = "isi_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_ISI,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk mmc1_clk = {
|
||||||
|
.name = "mci1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* emac1 clock - Only for sam9x25 */
|
||||||
|
static struct clk macb1_clk = {
|
||||||
|
.name = "pclk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk ssc_clk = {
|
||||||
|
.name = "ssc_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_SSC,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* can0 clock - Only for sam9x35 */
|
||||||
|
static struct clk can0_clk = {
|
||||||
|
.name = "can0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* can1 clock - Only for sam9x35 */
|
||||||
|
static struct clk can1_clk = {
|
||||||
|
.name = "can1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct clk *periph_clocks[] __initdata = {
|
||||||
|
&pioAB_clk,
|
||||||
|
&pioCD_clk,
|
||||||
|
&smd_clk,
|
||||||
|
&usart0_clk,
|
||||||
|
&usart1_clk,
|
||||||
|
&usart2_clk,
|
||||||
|
&twi0_clk,
|
||||||
|
&twi1_clk,
|
||||||
|
&twi2_clk,
|
||||||
|
&mmc0_clk,
|
||||||
|
&spi0_clk,
|
||||||
|
&spi1_clk,
|
||||||
|
&uart0_clk,
|
||||||
|
&uart1_clk,
|
||||||
|
&tcb0_clk,
|
||||||
|
&pwm_clk,
|
||||||
|
&adc_clk,
|
||||||
|
&dma0_clk,
|
||||||
|
&dma1_clk,
|
||||||
|
&uhphs_clk,
|
||||||
|
&udphs_clk,
|
||||||
|
&mmc1_clk,
|
||||||
|
&ssc_clk,
|
||||||
|
// irq0
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct clk_lookup periph_clocks_lookups[] = {
|
||||||
|
/* lookup table for DT entries */
|
||||||
|
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
|
||||||
|
CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
|
||||||
|
CLKDEV_CON_ID("pioA", &pioAB_clk),
|
||||||
|
CLKDEV_CON_ID("pioB", &pioAB_clk),
|
||||||
|
CLKDEV_CON_ID("pioC", &pioCD_clk),
|
||||||
|
CLKDEV_CON_ID("pioD", &pioCD_clk),
|
||||||
|
/* additional fake clock for macb_hclk */
|
||||||
|
CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The two programmable clocks.
|
||||||
|
* You must configure pin multiplexing to bring these signals out.
|
||||||
|
*/
|
||||||
|
static struct clk pck0 = {
|
||||||
|
.name = "pck0",
|
||||||
|
.pmc_mask = AT91_PMC_PCK0,
|
||||||
|
.type = CLK_TYPE_PROGRAMMABLE,
|
||||||
|
.id = 0,
|
||||||
|
};
|
||||||
|
static struct clk pck1 = {
|
||||||
|
.name = "pck1",
|
||||||
|
.pmc_mask = AT91_PMC_PCK1,
|
||||||
|
.type = CLK_TYPE_PROGRAMMABLE,
|
||||||
|
.id = 1,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void __init at91sam9x5_register_clocks(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
||||||
|
clk_register(periph_clocks[i]);
|
||||||
|
|
||||||
|
clkdev_add_table(periph_clocks_lookups,
|
||||||
|
ARRAY_SIZE(periph_clocks_lookups));
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9g25()
|
||||||
|
|| cpu_is_at91sam9x25())
|
||||||
|
clk_register(&usart3_clk);
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9g25()
|
||||||
|
|| cpu_is_at91sam9x25()
|
||||||
|
|| cpu_is_at91sam9g35()
|
||||||
|
|| cpu_is_at91sam9x35())
|
||||||
|
clk_register(&macb0_clk);
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9g15()
|
||||||
|
|| cpu_is_at91sam9g35()
|
||||||
|
|| cpu_is_at91sam9x35())
|
||||||
|
clk_register(&lcdc_clk);
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9g25())
|
||||||
|
clk_register(&isi_clk);
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9x25())
|
||||||
|
clk_register(&macb1_clk);
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9x25()
|
||||||
|
|| cpu_is_at91sam9x35()) {
|
||||||
|
clk_register(&can0_clk);
|
||||||
|
clk_register(&can1_clk);
|
||||||
|
}
|
||||||
|
|
||||||
|
clk_register(&pck0);
|
||||||
|
clk_register(&pck1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* AT91SAM9x5 processor initialization
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
static void __init at91sam9x5_map_io(void)
|
||||||
|
{
|
||||||
|
at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __init at91sam9x5_ioremap_registers(void)
|
||||||
|
{
|
||||||
|
if (of_at91sam926x_pit_init() < 0)
|
||||||
|
panic("Impossible to find PIT\n");
|
||||||
|
at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
|
||||||
|
}
|
||||||
|
|
||||||
|
void __init at91sam9x5_initialize(void)
|
||||||
|
{
|
||||||
|
arm_pm_restart = at91sam9g45_restart;
|
||||||
|
at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
|
||||||
|
|
||||||
|
/* Register GPIO subsystem (using DT) */
|
||||||
|
at91_gpio_init(NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* AT91SAM9x5 devices (temporary before modification of code)
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Interrupt initialization
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
/*
|
||||||
|
* The default interrupt priority levels (0 = lowest, 7 = highest).
|
||||||
|
*/
|
||||||
|
static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
||||||
|
7, /* Advanced Interrupt Controller (FIQ) */
|
||||||
|
7, /* System Peripherals */
|
||||||
|
1, /* Parallel IO Controller A and B */
|
||||||
|
1, /* Parallel IO Controller C and D */
|
||||||
|
4, /* Soft Modem */
|
||||||
|
5, /* USART 0 */
|
||||||
|
5, /* USART 1 */
|
||||||
|
5, /* USART 2 */
|
||||||
|
5, /* USART 3 */
|
||||||
|
6, /* Two-Wire Interface 0 */
|
||||||
|
6, /* Two-Wire Interface 1 */
|
||||||
|
6, /* Two-Wire Interface 2 */
|
||||||
|
0, /* Multimedia Card Interface 0 */
|
||||||
|
5, /* Serial Peripheral Interface 0 */
|
||||||
|
5, /* Serial Peripheral Interface 1 */
|
||||||
|
5, /* UART 0 */
|
||||||
|
5, /* UART 1 */
|
||||||
|
0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||||
|
0, /* Pulse Width Modulation Controller */
|
||||||
|
0, /* ADC Controller */
|
||||||
|
0, /* DMA Controller 0 */
|
||||||
|
0, /* DMA Controller 1 */
|
||||||
|
2, /* USB Host High Speed port */
|
||||||
|
2, /* USB Device High speed port */
|
||||||
|
3, /* Ethernet MAC 0 */
|
||||||
|
3, /* LDC Controller or Image Sensor Interface */
|
||||||
|
0, /* Multimedia Card Interface 1 */
|
||||||
|
3, /* Ethernet MAC 1 */
|
||||||
|
4, /* Synchronous Serial Interface */
|
||||||
|
4, /* CAN Controller 0 */
|
||||||
|
4, /* CAN Controller 1 */
|
||||||
|
0, /* Advanced Interrupt Controller (IRQ0) */
|
||||||
|
};
|
||||||
|
|
||||||
|
struct at91_init_soc __initdata at91sam9x5_soc = {
|
||||||
|
.map_io = at91sam9x5_map_io,
|
||||||
|
.default_irq_priority = at91sam9x5_default_irq_priority,
|
||||||
|
.ioremap_registers = at91sam9x5_ioremap_registers,
|
||||||
|
.register_clocks = at91sam9x5_register_clocks,
|
||||||
|
.init = at91sam9x5_initialize,
|
||||||
|
};
|
|
@ -13,6 +13,7 @@
|
||||||
#include <linux/kernel.h>
|
#include <linux/kernel.h>
|
||||||
#include <linux/init.h>
|
#include <linux/init.h>
|
||||||
#include <linux/irq.h>
|
#include <linux/irq.h>
|
||||||
|
#include <asm/proc-fns.h>
|
||||||
#include <asm/mach/arch.h>
|
#include <asm/mach/arch.h>
|
||||||
#include <mach/at91x40.h>
|
#include <mach/at91x40.h>
|
||||||
#include <mach/at91_st.h>
|
#include <mach/at91_st.h>
|
||||||
|
@ -37,8 +38,19 @@ unsigned long clk_get_rate(struct clk *clk)
|
||||||
return AT91X40_MASTER_CLOCK;
|
return AT91X40_MASTER_CLOCK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void at91x40_idle(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Disable the processor clock. The processor will be automatically
|
||||||
|
* re-enabled by an interrupt or by a reset.
|
||||||
|
*/
|
||||||
|
__raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
|
||||||
|
cpu_do_idle();
|
||||||
|
}
|
||||||
|
|
||||||
void __init at91x40_initialize(unsigned long main_clock)
|
void __init at91x40_initialize(unsigned long main_clock)
|
||||||
{
|
{
|
||||||
|
arm_pm_idle = at91x40_idle;
|
||||||
at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
|
at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
|
||||||
| (1 << AT91X40_ID_IRQ2);
|
| (1 << AT91X40_ID_IRQ2);
|
||||||
}
|
}
|
||||||
|
|
|
@ -28,6 +28,12 @@
|
||||||
#include <asm/mach/time.h>
|
#include <asm/mach/time.h>
|
||||||
#include <mach/at91_tc.h>
|
#include <mach/at91_tc.h>
|
||||||
|
|
||||||
|
#define at91_tc_read(field) \
|
||||||
|
__raw_readl(AT91_TC + field)
|
||||||
|
|
||||||
|
#define at91_tc_write(field, value) \
|
||||||
|
__raw_writel(value, AT91_TC + field);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 3 counter/timer units present.
|
* 3 counter/timer units present.
|
||||||
*/
|
*/
|
||||||
|
@ -37,12 +43,12 @@
|
||||||
|
|
||||||
static unsigned long at91x40_gettimeoffset(void)
|
static unsigned long at91x40_gettimeoffset(void)
|
||||||
{
|
{
|
||||||
return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
|
return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
|
||||||
}
|
}
|
||||||
|
|
||||||
static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
|
static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
|
||||||
{
|
{
|
||||||
at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
|
at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
|
||||||
timer_tick();
|
timer_tick();
|
||||||
return IRQ_HANDLED;
|
return IRQ_HANDLED;
|
||||||
}
|
}
|
||||||
|
@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
|
||||||
{
|
{
|
||||||
unsigned int v;
|
unsigned int v;
|
||||||
|
|
||||||
at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
|
at91_tc_write(AT91_TC_BCR, 0);
|
||||||
v = at91_sys_read(AT91_TC + AT91_TC_BMR);
|
v = at91_tc_read(AT91_TC_BMR);
|
||||||
v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
|
v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
|
||||||
at91_sys_write(AT91_TC + AT91_TC_BMR, v);
|
at91_tc_write(AT91_TC_BMR, v);
|
||||||
|
|
||||||
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
|
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
|
||||||
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
|
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
|
||||||
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
|
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
|
||||||
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
|
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
|
||||||
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
|
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
|
||||||
|
|
||||||
setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
|
setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
|
||||||
|
|
||||||
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
|
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
|
||||||
}
|
}
|
||||||
|
|
||||||
struct sys_timer at91x40_timer = {
|
struct sys_timer at91x40_timer = {
|
||||||
|
|
|
@ -1,396 +0,0 @@
|
||||||
/*
|
|
||||||
* linux/arch/arm/mach-at91/board-cap9adk.c
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
|
|
||||||
* Copyright (C) 2005 SAN People
|
|
||||||
* Copyright (C) 2007 Atmel Corporation.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/types.h>
|
|
||||||
#include <linux/gpio.h>
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/mm.h>
|
|
||||||
#include <linux/module.h>
|
|
||||||
#include <linux/platform_device.h>
|
|
||||||
#include <linux/spi/spi.h>
|
|
||||||
#include <linux/spi/ads7846.h>
|
|
||||||
#include <linux/fb.h>
|
|
||||||
#include <linux/mtd/physmap.h>
|
|
||||||
|
|
||||||
#include <video/atmel_lcdc.h>
|
|
||||||
|
|
||||||
#include <mach/hardware.h>
|
|
||||||
#include <asm/setup.h>
|
|
||||||
#include <asm/mach-types.h>
|
|
||||||
|
|
||||||
#include <asm/mach/arch.h>
|
|
||||||
#include <asm/mach/map.h>
|
|
||||||
|
|
||||||
#include <mach/board.h>
|
|
||||||
#include <mach/at91cap9_matrix.h>
|
|
||||||
#include <mach/at91sam9_smc.h>
|
|
||||||
#include <mach/system_rev.h>
|
|
||||||
|
|
||||||
#include "sam9_smc.h"
|
|
||||||
#include "generic.h"
|
|
||||||
|
|
||||||
|
|
||||||
static void __init cap9adk_init_early(void)
|
|
||||||
{
|
|
||||||
/* Initialize processor: 12 MHz crystal */
|
|
||||||
at91_initialize(12000000);
|
|
||||||
|
|
||||||
/* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */
|
|
||||||
at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11);
|
|
||||||
/* ... POWER LED always on */
|
|
||||||
at91_set_gpio_output(AT91_PIN_PC29, 1);
|
|
||||||
|
|
||||||
/* Setup the serial ports and console */
|
|
||||||
at91_register_uart(0, 0, 0); /* DBGU = ttyS0 */
|
|
||||||
at91_set_serial_console(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* USB Host port
|
|
||||||
*/
|
|
||||||
static struct at91_usbh_data __initdata cap9adk_usbh_data = {
|
|
||||||
.ports = 2,
|
|
||||||
.vbus_pin = {-EINVAL, -EINVAL},
|
|
||||||
.overcurrent_pin= {-EINVAL, -EINVAL},
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* USB HS Device port
|
|
||||||
*/
|
|
||||||
static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
|
|
||||||
.vbus_pin = AT91_PIN_PB31,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* ADS7846 Touchscreen
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
|
|
||||||
static int ads7843_pendown_state(void)
|
|
||||||
{
|
|
||||||
return !at91_get_gpio_value(AT91_PIN_PC4); /* Touchscreen PENIRQ */
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct ads7846_platform_data ads_info = {
|
|
||||||
.model = 7843,
|
|
||||||
.x_min = 150,
|
|
||||||
.x_max = 3830,
|
|
||||||
.y_min = 190,
|
|
||||||
.y_max = 3830,
|
|
||||||
.vref_delay_usecs = 100,
|
|
||||||
.x_plate_ohms = 450,
|
|
||||||
.y_plate_ohms = 250,
|
|
||||||
.pressure_max = 15000,
|
|
||||||
.debounce_max = 1,
|
|
||||||
.debounce_rep = 0,
|
|
||||||
.debounce_tol = (~0),
|
|
||||||
.get_pendown_state = ads7843_pendown_state,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init cap9adk_add_device_ts(void)
|
|
||||||
{
|
|
||||||
at91_set_gpio_input(AT91_PIN_PC4, 1); /* Touchscreen PENIRQ */
|
|
||||||
at91_set_gpio_input(AT91_PIN_PC5, 1); /* Touchscreen BUSY */
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
static void __init cap9adk_add_device_ts(void) {}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SPI devices.
|
|
||||||
*/
|
|
||||||
static struct spi_board_info cap9adk_spi_devices[] = {
|
|
||||||
#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
|
|
||||||
{ /* DataFlash card */
|
|
||||||
.modalias = "mtd_dataflash",
|
|
||||||
.chip_select = 0,
|
|
||||||
.max_speed_hz = 15 * 1000 * 1000,
|
|
||||||
.bus_num = 0,
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
|
|
||||||
{
|
|
||||||
.modalias = "ads7846",
|
|
||||||
.chip_select = 3, /* can be 2 or 3, depending on J2 jumper */
|
|
||||||
.max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
|
|
||||||
.bus_num = 0,
|
|
||||||
.platform_data = &ads_info,
|
|
||||||
.irq = AT91_PIN_PC4,
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MCI (SD/MMC)
|
|
||||||
*/
|
|
||||||
static struct at91_mmc_data __initdata cap9adk_mmc_data = {
|
|
||||||
.wire4 = 1,
|
|
||||||
.det_pin = -EINVAL,
|
|
||||||
.wp_pin = -EINVAL,
|
|
||||||
.vcc_pin = -EINVAL,
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MACB Ethernet device
|
|
||||||
*/
|
|
||||||
static struct macb_platform_data __initdata cap9adk_macb_data = {
|
|
||||||
.phy_irq_pin = -EINVAL,
|
|
||||||
.is_rmii = 1,
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NAND flash
|
|
||||||
*/
|
|
||||||
static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
|
|
||||||
{
|
|
||||||
.name = "NAND partition",
|
|
||||||
.offset = 0,
|
|
||||||
.size = MTDPART_SIZ_FULL,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct atmel_nand_data __initdata cap9adk_nand_data = {
|
|
||||||
.ale = 21,
|
|
||||||
.cle = 22,
|
|
||||||
.det_pin = -EINVAL,
|
|
||||||
.rdy_pin = -EINVAL,
|
|
||||||
.enable_pin = AT91_PIN_PD15,
|
|
||||||
.parts = cap9adk_nand_partitions,
|
|
||||||
.num_parts = ARRAY_SIZE(cap9adk_nand_partitions),
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct sam9_smc_config __initdata cap9adk_nand_smc_config = {
|
|
||||||
.ncs_read_setup = 1,
|
|
||||||
.nrd_setup = 2,
|
|
||||||
.ncs_write_setup = 1,
|
|
||||||
.nwe_setup = 2,
|
|
||||||
|
|
||||||
.ncs_read_pulse = 6,
|
|
||||||
.nrd_pulse = 4,
|
|
||||||
.ncs_write_pulse = 6,
|
|
||||||
.nwe_pulse = 4,
|
|
||||||
|
|
||||||
.read_cycle = 8,
|
|
||||||
.write_cycle = 8,
|
|
||||||
|
|
||||||
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
|
|
||||||
.tdf_cycles = 1,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init cap9adk_add_device_nand(void)
|
|
||||||
{
|
|
||||||
unsigned long csa;
|
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
|
||||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
|
|
||||||
|
|
||||||
cap9adk_nand_data.bus_width_16 = board_have_nand_16bit();
|
|
||||||
/* setup bus-width (8 or 16) */
|
|
||||||
if (cap9adk_nand_data.bus_width_16)
|
|
||||||
cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16;
|
|
||||||
else
|
|
||||||
cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
|
|
||||||
|
|
||||||
/* configure chip-select 3 (NAND) */
|
|
||||||
sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
|
|
||||||
|
|
||||||
at91_add_device_nand(&cap9adk_nand_data);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NOR flash
|
|
||||||
*/
|
|
||||||
static struct mtd_partition cap9adk_nor_partitions[] = {
|
|
||||||
{
|
|
||||||
.name = "NOR partition",
|
|
||||||
.offset = 0,
|
|
||||||
.size = MTDPART_SIZ_FULL,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct physmap_flash_data cap9adk_nor_data = {
|
|
||||||
.width = 2,
|
|
||||||
.parts = cap9adk_nor_partitions,
|
|
||||||
.nr_parts = ARRAY_SIZE(cap9adk_nor_partitions),
|
|
||||||
};
|
|
||||||
|
|
||||||
#define NOR_BASE AT91_CHIPSELECT_0
|
|
||||||
#define NOR_SIZE SZ_8M
|
|
||||||
|
|
||||||
static struct resource nor_flash_resources[] = {
|
|
||||||
{
|
|
||||||
.start = NOR_BASE,
|
|
||||||
.end = NOR_BASE + NOR_SIZE - 1,
|
|
||||||
.flags = IORESOURCE_MEM,
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct platform_device cap9adk_nor_flash = {
|
|
||||||
.name = "physmap-flash",
|
|
||||||
.id = 0,
|
|
||||||
.dev = {
|
|
||||||
.platform_data = &cap9adk_nor_data,
|
|
||||||
},
|
|
||||||
.resource = nor_flash_resources,
|
|
||||||
.num_resources = ARRAY_SIZE(nor_flash_resources),
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct sam9_smc_config __initdata cap9adk_nor_smc_config = {
|
|
||||||
.ncs_read_setup = 2,
|
|
||||||
.nrd_setup = 4,
|
|
||||||
.ncs_write_setup = 2,
|
|
||||||
.nwe_setup = 4,
|
|
||||||
|
|
||||||
.ncs_read_pulse = 10,
|
|
||||||
.nrd_pulse = 8,
|
|
||||||
.ncs_write_pulse = 10,
|
|
||||||
.nwe_pulse = 8,
|
|
||||||
|
|
||||||
.read_cycle = 16,
|
|
||||||
.write_cycle = 16,
|
|
||||||
|
|
||||||
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
|
|
||||||
.tdf_cycles = 1,
|
|
||||||
};
|
|
||||||
|
|
||||||
static __init void cap9adk_add_device_nor(void)
|
|
||||||
{
|
|
||||||
unsigned long csa;
|
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
|
||||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
|
|
||||||
|
|
||||||
/* configure chip-select 0 (NOR) */
|
|
||||||
sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
|
|
||||||
|
|
||||||
platform_device_register(&cap9adk_nor_flash);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* LCD Controller
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
|
|
||||||
static struct fb_videomode at91_tft_vga_modes[] = {
|
|
||||||
{
|
|
||||||
.name = "TX09D50VM1CCA @ 60",
|
|
||||||
.refresh = 60,
|
|
||||||
.xres = 240, .yres = 320,
|
|
||||||
.pixclock = KHZ2PICOS(4965),
|
|
||||||
|
|
||||||
.left_margin = 1, .right_margin = 33,
|
|
||||||
.upper_margin = 1, .lower_margin = 0,
|
|
||||||
.hsync_len = 5, .vsync_len = 1,
|
|
||||||
|
|
||||||
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
|
|
||||||
.vmode = FB_VMODE_NONINTERLACED,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct fb_monspecs at91fb_default_monspecs = {
|
|
||||||
.manufacturer = "HIT",
|
|
||||||
.monitor = "TX09D70VM1CCA",
|
|
||||||
|
|
||||||
.modedb = at91_tft_vga_modes,
|
|
||||||
.modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
|
|
||||||
.hfmin = 15000,
|
|
||||||
.hfmax = 64000,
|
|
||||||
.vfmin = 50,
|
|
||||||
.vfmax = 150,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define AT91CAP9_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
|
|
||||||
| ATMEL_LCDC_DISTYPE_TFT \
|
|
||||||
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
|
|
||||||
|
|
||||||
static void at91_lcdc_power_control(int on)
|
|
||||||
{
|
|
||||||
if (on)
|
|
||||||
at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
|
|
||||||
else
|
|
||||||
at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Driver datas */
|
|
||||||
static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data = {
|
|
||||||
.default_bpp = 16,
|
|
||||||
.default_dmacon = ATMEL_LCDC_DMAEN,
|
|
||||||
.default_lcdcon2 = AT91CAP9_DEFAULT_LCDCON2,
|
|
||||||
.default_monspecs = &at91fb_default_monspecs,
|
|
||||||
.atmel_lcdfb_power_control = at91_lcdc_power_control,
|
|
||||||
.guard_time = 1,
|
|
||||||
};
|
|
||||||
|
|
||||||
#else
|
|
||||||
static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* AC97
|
|
||||||
*/
|
|
||||||
static struct ac97c_platform_data cap9adk_ac97_data = {
|
|
||||||
.reset_pin = -EINVAL,
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
static void __init cap9adk_board_init(void)
|
|
||||||
{
|
|
||||||
/* Serial */
|
|
||||||
at91_add_device_serial();
|
|
||||||
/* USB Host */
|
|
||||||
at91_add_device_usbh(&cap9adk_usbh_data);
|
|
||||||
/* USB HS */
|
|
||||||
at91_add_device_usba(&cap9adk_usba_udc_data);
|
|
||||||
/* SPI */
|
|
||||||
at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
|
|
||||||
/* Touchscreen */
|
|
||||||
cap9adk_add_device_ts();
|
|
||||||
/* MMC */
|
|
||||||
at91_add_device_mmc(1, &cap9adk_mmc_data);
|
|
||||||
/* Ethernet */
|
|
||||||
at91_add_device_eth(&cap9adk_macb_data);
|
|
||||||
/* NAND */
|
|
||||||
cap9adk_add_device_nand();
|
|
||||||
/* NOR Flash */
|
|
||||||
cap9adk_add_device_nor();
|
|
||||||
/* I2C */
|
|
||||||
at91_add_device_i2c(NULL, 0);
|
|
||||||
/* LCD Controller */
|
|
||||||
at91_add_device_lcdc(&cap9adk_lcdc_data);
|
|
||||||
/* AC97 */
|
|
||||||
at91_add_device_ac97(&cap9adk_ac97_data);
|
|
||||||
}
|
|
||||||
|
|
||||||
MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
|
|
||||||
/* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
|
|
||||||
.timer = &at91sam926x_timer,
|
|
||||||
.map_io = at91_map_io,
|
|
||||||
.init_early = cap9adk_init_early,
|
|
||||||
.init_irq = at91_init_irq_default,
|
|
||||||
.init_machine = cap9adk_board_init,
|
|
||||||
MACHINE_END
|
|
|
@ -43,6 +43,7 @@
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91sam9_smc.h>
|
#include <mach/at91sam9_smc.h>
|
||||||
#include <mach/at91sam9260_matrix.h>
|
#include <mach/at91sam9260_matrix.h>
|
||||||
|
#include <mach/at91_matrix.h>
|
||||||
|
|
||||||
#include "sam9_smc.h"
|
#include "sam9_smc.h"
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void)
|
||||||
{
|
{
|
||||||
unsigned long csa;
|
unsigned long csa;
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
|
||||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
|
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
|
||||||
|
|
||||||
/* configure chip-select 0 (NOR) */
|
/* configure chip-select 0 (NOR) */
|
||||||
sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
|
sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
|
||||||
|
|
|
@ -38,6 +38,7 @@
|
||||||
|
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91rm9200_mc.h>
|
#include <mach/at91rm9200_mc.h>
|
||||||
|
#include <mach/at91_ramc.h>
|
||||||
#include <mach/cpu.h>
|
#include <mach/cpu.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
|
|
@ -38,12 +38,6 @@ static void __init ek_init_early(void)
|
||||||
{
|
{
|
||||||
/* Initialize processor: 12.000 MHz crystal */
|
/* Initialize processor: 12.000 MHz crystal */
|
||||||
at91_initialize(12000000);
|
at91_initialize(12000000);
|
||||||
|
|
||||||
/* DGBU on ttyS0. (Rx & Tx only) */
|
|
||||||
at91_register_uart(0, 0, 0);
|
|
||||||
|
|
||||||
/* set serial console to ttyS0 (ie, DBGU) */
|
|
||||||
at91_set_serial_console(0);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* det_pin is not connected */
|
/* det_pin is not connected */
|
||||||
|
@ -109,6 +103,7 @@ static void __init at91_dt_device_init(void)
|
||||||
|
|
||||||
static const char *at91_dt_board_compat[] __initdata = {
|
static const char *at91_dt_board_compat[] __initdata = {
|
||||||
"atmel,at91sam9m10g45ek",
|
"atmel,at91sam9m10g45ek",
|
||||||
|
"atmel,at91sam9x5ek",
|
||||||
"calao,usb-a9g20",
|
"calao,usb-a9g20",
|
||||||
NULL
|
NULL
|
||||||
};
|
};
|
||||||
|
|
|
@ -26,6 +26,7 @@
|
||||||
|
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91rm9200_mc.h>
|
#include <mach/at91rm9200_mc.h>
|
||||||
|
#include <mach/at91_ramc.h>
|
||||||
#include <mach/cpu.h>
|
#include <mach/cpu.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
@ -110,7 +111,7 @@ static void __init eco920_board_init(void)
|
||||||
at91_add_device_mmc(0, &eco920_mmc_data);
|
at91_add_device_mmc(0, &eco920_mmc_data);
|
||||||
platform_device_register(&eco920_flash);
|
platform_device_register(&eco920_flash);
|
||||||
|
|
||||||
at91_sys_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
|
at91_ramc_write(0, AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
|
||||||
| AT91_SMC_RWSETUP_(1)
|
| AT91_SMC_RWSETUP_(1)
|
||||||
| AT91_SMC_DBW_8
|
| AT91_SMC_DBW_8
|
||||||
| AT91_SMC_WSEN
|
| AT91_SMC_WSEN
|
||||||
|
@ -122,7 +123,7 @@ static void __init eco920_board_init(void)
|
||||||
at91_set_deglitch(AT91_PIN_PA23, 1);
|
at91_set_deglitch(AT91_PIN_PA23, 1);
|
||||||
|
|
||||||
/* Initialization of the Static Memory Controller for Chip Select 3 */
|
/* Initialization of the Static Memory Controller for Chip Select 3 */
|
||||||
at91_sys_write(AT91_SMC_CSR(3),
|
at91_ramc_write(0, AT91_SMC_CSR(3),
|
||||||
AT91_SMC_DBW_16 | /* 16 bit */
|
AT91_SMC_DBW_16 | /* 16 bit */
|
||||||
AT91_SMC_WSEN |
|
AT91_SMC_WSEN |
|
||||||
AT91_SMC_NWS_(5) | /* wait states */
|
AT91_SMC_NWS_(5) | /* wait states */
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* linux/arch/arm/mach-at91/board-flexibity.c
|
* linux/arch/arm/mach-at91/board-flexibity.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2010 Flexibity
|
* Copyright (C) 2010-2011 Flexibity
|
||||||
* Copyright (C) 2005 SAN People
|
* Copyright (C) 2005 SAN People
|
||||||
* Copyright (C) 2006 Atmel
|
* Copyright (C) 2006 Atmel
|
||||||
*
|
*
|
||||||
|
@ -62,6 +62,13 @@ static struct at91_udc_data __initdata flexibity_udc_data = {
|
||||||
.pullup_pin = -EINVAL, /* pull-up driven by UDC */
|
.pullup_pin = -EINVAL, /* pull-up driven by UDC */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* I2C devices */
|
||||||
|
static struct i2c_board_info __initdata flexibity_i2c_devices[] = {
|
||||||
|
{
|
||||||
|
I2C_BOARD_INFO("ds1307", 0x68),
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
/* SPI devices */
|
/* SPI devices */
|
||||||
static struct spi_board_info flexibity_spi_devices[] = {
|
static struct spi_board_info flexibity_spi_devices[] = {
|
||||||
{ /* DataFlash chip */
|
{ /* DataFlash chip */
|
||||||
|
@ -141,6 +148,9 @@ static void __init flexibity_board_init(void)
|
||||||
at91_add_device_usbh(&flexibity_usbh_data);
|
at91_add_device_usbh(&flexibity_usbh_data);
|
||||||
/* USB Device */
|
/* USB Device */
|
||||||
at91_add_device_udc(&flexibity_udc_data);
|
at91_add_device_udc(&flexibity_udc_data);
|
||||||
|
/* I2C */
|
||||||
|
at91_add_device_i2c(flexibity_i2c_devices,
|
||||||
|
ARRAY_SIZE(flexibity_i2c_devices));
|
||||||
/* SPI */
|
/* SPI */
|
||||||
at91_add_device_spi(flexibity_spi_devices,
|
at91_add_device_spi(flexibity_spi_devices,
|
||||||
ARRAY_SIZE(flexibity_spi_devices));
|
ARRAY_SIZE(flexibity_spi_devices));
|
||||||
|
|
|
@ -38,6 +38,7 @@
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/cpu.h>
|
#include <mach/cpu.h>
|
||||||
#include <mach/at91rm9200_mc.h>
|
#include <mach/at91rm9200_mc.h>
|
||||||
|
#include <mach/at91_ramc.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
|
||||||
|
|
|
@ -39,6 +39,7 @@
|
||||||
|
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91rm9200_mc.h>
|
#include <mach/at91rm9200_mc.h>
|
||||||
|
#include <mach/at91_ramc.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
|
||||||
|
|
|
@ -41,6 +41,7 @@
|
||||||
#include <mach/hardware.h>
|
#include <mach/hardware.h>
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91rm9200_mc.h>
|
#include <mach/at91rm9200_mc.h>
|
||||||
|
#include <mach/at91_ramc.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
|
||||||
|
|
|
@ -41,6 +41,7 @@
|
||||||
#include <mach/hardware.h>
|
#include <mach/hardware.h>
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91rm9200_mc.h>
|
#include <mach/at91rm9200_mc.h>
|
||||||
|
#include <mach/at91_ramc.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
|
||||||
|
|
|
@ -24,11 +24,13 @@
|
||||||
#include <linux/gpio_keys.h>
|
#include <linux/gpio_keys.h>
|
||||||
#include <linux/input.h>
|
#include <linux/input.h>
|
||||||
#include <linux/leds.h>
|
#include <linux/leds.h>
|
||||||
#include <linux/clk.h>
|
|
||||||
#include <linux/atmel-mci.h>
|
#include <linux/atmel-mci.h>
|
||||||
|
#include <linux/delay.h>
|
||||||
|
|
||||||
#include <mach/hardware.h>
|
#include <mach/hardware.h>
|
||||||
#include <video/atmel_lcdc.h>
|
#include <video/atmel_lcdc.h>
|
||||||
|
#include <media/soc_camera.h>
|
||||||
|
#include <media/atmel-isi.h>
|
||||||
|
|
||||||
#include <asm/setup.h>
|
#include <asm/setup.h>
|
||||||
#include <asm/mach-types.h>
|
#include <asm/mach-types.h>
|
||||||
|
@ -184,6 +186,71 @@ static void __init ek_add_device_nand(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ISI
|
||||||
|
*/
|
||||||
|
static struct isi_platform_data __initdata isi_data = {
|
||||||
|
.frate = ISI_CFG1_FRATE_CAPTURE_ALL,
|
||||||
|
/* to use codec and preview path simultaneously */
|
||||||
|
.full_mode = 1,
|
||||||
|
.data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
|
||||||
|
/* ISI_MCK is provided by programmable clock or external clock */
|
||||||
|
.mck_hz = 25000000,
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* soc-camera OV2640
|
||||||
|
*/
|
||||||
|
#if defined(CONFIG_SOC_CAMERA_OV2640) || \
|
||||||
|
defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
|
||||||
|
static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
|
||||||
|
{
|
||||||
|
/* ISI board for ek using default 8-bits connection */
|
||||||
|
return SOCAM_DATAWIDTH_8;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int i2c_camera_power(struct device *dev, int on)
|
||||||
|
{
|
||||||
|
/* enable or disable the camera */
|
||||||
|
pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
|
||||||
|
at91_set_gpio_output(AT91_PIN_PD13, !on);
|
||||||
|
|
||||||
|
if (!on)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
/* If enabled, give a reset impulse */
|
||||||
|
at91_set_gpio_output(AT91_PIN_PD12, 0);
|
||||||
|
msleep(20);
|
||||||
|
at91_set_gpio_output(AT91_PIN_PD12, 1);
|
||||||
|
msleep(100);
|
||||||
|
|
||||||
|
out:
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct i2c_board_info i2c_camera = {
|
||||||
|
I2C_BOARD_INFO("ov2640", 0x30),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct soc_camera_link iclink_ov2640 = {
|
||||||
|
.bus_id = 0,
|
||||||
|
.board_info = &i2c_camera,
|
||||||
|
.i2c_adapter_id = 0,
|
||||||
|
.power = i2c_camera_power,
|
||||||
|
.query_bus_param = isi_camera_query_bus_param,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device isi_ov2640 = {
|
||||||
|
.name = "soc-camera-pdrv",
|
||||||
|
.id = 0,
|
||||||
|
.dev = {
|
||||||
|
.platform_data = &iclink_ov2640,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* LCD Controller
|
* LCD Controller
|
||||||
*/
|
*/
|
||||||
|
@ -377,7 +444,12 @@ static struct gpio_led ek_pwm_led[] = {
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct platform_device *devices[] __initdata = {
|
||||||
|
#if defined(CONFIG_SOC_CAMERA_OV2640) || \
|
||||||
|
defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
|
||||||
|
&isi_ov2640,
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
static void __init ek_board_init(void)
|
static void __init ek_board_init(void)
|
||||||
{
|
{
|
||||||
|
@ -399,6 +471,8 @@ static void __init ek_board_init(void)
|
||||||
ek_add_device_nand();
|
ek_add_device_nand();
|
||||||
/* I2C */
|
/* I2C */
|
||||||
at91_add_device_i2c(0, NULL, 0);
|
at91_add_device_i2c(0, NULL, 0);
|
||||||
|
/* ISI, using programmable clock as ISI_MCK */
|
||||||
|
at91_add_device_isi(&isi_data, true);
|
||||||
/* LCD Controller */
|
/* LCD Controller */
|
||||||
at91_add_device_lcdc(&ek_lcdc_data);
|
at91_add_device_lcdc(&ek_lcdc_data);
|
||||||
/* Touch Screen */
|
/* Touch Screen */
|
||||||
|
@ -410,6 +484,8 @@ static void __init ek_board_init(void)
|
||||||
/* LEDs */
|
/* LEDs */
|
||||||
at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
|
at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
|
||||||
at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
|
at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
|
||||||
|
/* Other platform devices */
|
||||||
|
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||||
}
|
}
|
||||||
|
|
||||||
MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
|
MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
|
||||||
|
|
|
@ -45,6 +45,7 @@
|
||||||
#include <mach/hardware.h>
|
#include <mach/hardware.h>
|
||||||
#include <mach/board.h>
|
#include <mach/board.h>
|
||||||
#include <mach/at91rm9200_mc.h>
|
#include <mach/at91rm9200_mc.h>
|
||||||
|
#include <mach/at91_ramc.h>
|
||||||
#include <mach/cpu.h>
|
#include <mach/cpu.h>
|
||||||
|
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
@ -393,7 +394,7 @@ static void yl9200_init_video(void)
|
||||||
at91_set_A_periph(AT91_PIN_PC6, 0);
|
at91_set_A_periph(AT91_PIN_PC6, 0);
|
||||||
|
|
||||||
/* Initialization of the Static Memory Controller for Chip Select 2 */
|
/* Initialization of the Static Memory Controller for Chip Select 2 */
|
||||||
at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
|
at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
|
||||||
| AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
|
| AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
|
||||||
| AT91_SMC_TDF_(0x100) /* float time */
|
| AT91_SMC_TDF_(0x100) /* float time */
|
||||||
);
|
);
|
||||||
|
|
|
@ -28,9 +28,12 @@
|
||||||
#include <mach/at91_pmc.h>
|
#include <mach/at91_pmc.h>
|
||||||
#include <mach/cpu.h>
|
#include <mach/cpu.h>
|
||||||
|
|
||||||
|
#include <asm/proc-fns.h>
|
||||||
|
|
||||||
#include "clock.h"
|
#include "clock.h"
|
||||||
#include "generic.h"
|
#include "generic.h"
|
||||||
|
|
||||||
|
void __iomem *at91_pmc_base;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* There's a lot more which can be done with clocks, including cpufreq
|
* There's a lot more which can be done with clocks, including cpufreq
|
||||||
|
@ -47,26 +50,38 @@
|
||||||
/*
|
/*
|
||||||
* Chips have some kind of clocks : group them by functionality
|
* Chips have some kind of clocks : group them by functionality
|
||||||
*/
|
*/
|
||||||
#define cpu_has_utmi() ( cpu_is_at91cap9() \
|
#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
|
||||||
|| cpu_is_at91sam9rl() \
|
|| cpu_is_at91sam9g45() \
|
||||||
|| cpu_is_at91sam9g45())
|
|| cpu_is_at91sam9x5())
|
||||||
|
|
||||||
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|
||||||
|| cpu_is_at91sam9g45())
|
|| cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5())
|
||||||
|
|
||||||
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
|
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
|
||||||
|
|
||||||
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|
||||||
|| cpu_is_at91sam9g45()))
|
|| cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5()))
|
||||||
|
|
||||||
#define cpu_has_upll() (cpu_is_at91sam9g45())
|
#define cpu_has_upll() (cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5())
|
||||||
|
|
||||||
/* USB host HS & FS */
|
/* USB host HS & FS */
|
||||||
#define cpu_has_uhp() (!cpu_is_at91sam9rl())
|
#define cpu_has_uhp() (!cpu_is_at91sam9rl())
|
||||||
|
|
||||||
/* USB device FS only */
|
/* USB device FS only */
|
||||||
#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
|
#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
|
||||||
|| cpu_is_at91sam9g45()))
|
|| cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5()))
|
||||||
|
|
||||||
|
#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5())
|
||||||
|
|
||||||
|
#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5())
|
||||||
|
|
||||||
|
#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
|
||||||
|
|
||||||
static LIST_HEAD(clocks);
|
static LIST_HEAD(clocks);
|
||||||
static DEFINE_SPINLOCK(clk_lock);
|
static DEFINE_SPINLOCK(clk_lock);
|
||||||
|
@ -111,11 +126,11 @@ static void pllb_mode(struct clk *clk, int is_on)
|
||||||
value = 0;
|
value = 0;
|
||||||
|
|
||||||
// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
|
// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
|
||||||
at91_sys_write(AT91_CKGR_PLLBR, value);
|
at91_pmc_write(AT91_CKGR_PLLBR, value);
|
||||||
|
|
||||||
do {
|
do {
|
||||||
cpu_relax();
|
cpu_relax();
|
||||||
} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
|
} while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct clk pllb = {
|
static struct clk pllb = {
|
||||||
|
@ -130,31 +145,24 @@ static struct clk pllb = {
|
||||||
static void pmc_sys_mode(struct clk *clk, int is_on)
|
static void pmc_sys_mode(struct clk *clk, int is_on)
|
||||||
{
|
{
|
||||||
if (is_on)
|
if (is_on)
|
||||||
at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
|
at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
|
||||||
else
|
else
|
||||||
at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
|
at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void pmc_uckr_mode(struct clk *clk, int is_on)
|
static void pmc_uckr_mode(struct clk *clk, int is_on)
|
||||||
{
|
{
|
||||||
unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
|
unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
|
||||||
|
|
||||||
if (cpu_is_at91sam9g45()) {
|
|
||||||
if (is_on)
|
|
||||||
uckr |= AT91_PMC_BIASEN;
|
|
||||||
else
|
|
||||||
uckr &= ~AT91_PMC_BIASEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (is_on) {
|
if (is_on) {
|
||||||
is_on = AT91_PMC_LOCKU;
|
is_on = AT91_PMC_LOCKU;
|
||||||
at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
|
at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
|
||||||
} else
|
} else
|
||||||
at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
|
at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
|
||||||
|
|
||||||
do {
|
do {
|
||||||
cpu_relax();
|
cpu_relax();
|
||||||
} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
|
} while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* USB function clocks (PLLB must be 48 MHz) */
|
/* USB function clocks (PLLB must be 48 MHz) */
|
||||||
|
@ -190,9 +198,9 @@ struct clk mck = {
|
||||||
static void pmc_periph_mode(struct clk *clk, int is_on)
|
static void pmc_periph_mode(struct clk *clk, int is_on)
|
||||||
{
|
{
|
||||||
if (is_on)
|
if (is_on)
|
||||||
at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
|
at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
|
||||||
else
|
else
|
||||||
at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
|
at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct clk __init *at91_css_to_clk(unsigned long css)
|
static struct clk __init *at91_css_to_clk(unsigned long css)
|
||||||
|
@ -210,11 +218,24 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
|
||||||
return &utmi_clk;
|
return &utmi_clk;
|
||||||
else if (cpu_has_pllb())
|
else if (cpu_has_pllb())
|
||||||
return &pllb;
|
return &pllb;
|
||||||
|
break;
|
||||||
|
/* alternate PMC: can use master clock */
|
||||||
|
case AT91_PMC_CSS_MASTER:
|
||||||
|
return &mck;
|
||||||
}
|
}
|
||||||
|
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int pmc_prescaler_divider(u32 reg)
|
||||||
|
{
|
||||||
|
if (cpu_has_alt_prescaler()) {
|
||||||
|
return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
|
||||||
|
} else {
|
||||||
|
return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
static void __clk_enable(struct clk *clk)
|
static void __clk_enable(struct clk *clk)
|
||||||
{
|
{
|
||||||
if (clk->parent)
|
if (clk->parent)
|
||||||
|
@ -316,12 +337,22 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||||
{
|
{
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
unsigned prescale;
|
unsigned prescale;
|
||||||
|
unsigned long prescale_offset, css_mask;
|
||||||
unsigned long actual;
|
unsigned long actual;
|
||||||
|
|
||||||
if (!clk_is_programmable(clk))
|
if (!clk_is_programmable(clk))
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
if (clk->users)
|
if (clk->users)
|
||||||
return -EBUSY;
|
return -EBUSY;
|
||||||
|
|
||||||
|
if (cpu_has_alt_prescaler()) {
|
||||||
|
prescale_offset = PMC_ALT_PRES_OFFSET;
|
||||||
|
css_mask = AT91_PMC_ALT_PCKR_CSS;
|
||||||
|
} else {
|
||||||
|
prescale_offset = PMC_PRES_OFFSET;
|
||||||
|
css_mask = AT91_PMC_CSS;
|
||||||
|
}
|
||||||
|
|
||||||
spin_lock_irqsave(&clk_lock, flags);
|
spin_lock_irqsave(&clk_lock, flags);
|
||||||
|
|
||||||
actual = clk->parent->rate_hz;
|
actual = clk->parent->rate_hz;
|
||||||
|
@ -329,10 +360,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||||
if (actual && actual <= rate) {
|
if (actual && actual <= rate) {
|
||||||
u32 pckr;
|
u32 pckr;
|
||||||
|
|
||||||
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
|
||||||
pckr &= AT91_PMC_CSS; /* clock selection */
|
pckr &= css_mask; /* keep clock selection */
|
||||||
pckr |= prescale << 2;
|
pckr |= prescale << prescale_offset;
|
||||||
at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
|
at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
|
||||||
clk->rate_hz = actual;
|
clk->rate_hz = actual;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -366,7 +397,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||||
|
|
||||||
clk->rate_hz = parent->rate_hz;
|
clk->rate_hz = parent->rate_hz;
|
||||||
clk->parent = parent;
|
clk->parent = parent;
|
||||||
at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
|
at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
|
||||||
|
|
||||||
spin_unlock_irqrestore(&clk_lock, flags);
|
spin_unlock_irqrestore(&clk_lock, flags);
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -378,11 +409,17 @@ static void __init init_programmable_clock(struct clk *clk)
|
||||||
{
|
{
|
||||||
struct clk *parent;
|
struct clk *parent;
|
||||||
u32 pckr;
|
u32 pckr;
|
||||||
|
unsigned int css_mask;
|
||||||
|
|
||||||
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
if (cpu_has_alt_prescaler())
|
||||||
parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
|
css_mask = AT91_PMC_ALT_PCKR_CSS;
|
||||||
|
else
|
||||||
|
css_mask = AT91_PMC_CSS;
|
||||||
|
|
||||||
|
pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
|
||||||
|
parent = at91_css_to_clk(pckr & css_mask);
|
||||||
clk->parent = parent;
|
clk->parent = parent;
|
||||||
clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
|
clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
|
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
|
||||||
|
@ -396,19 +433,24 @@ static int at91_clk_show(struct seq_file *s, void *unused)
|
||||||
u32 scsr, pcsr, uckr = 0, sr;
|
u32 scsr, pcsr, uckr = 0, sr;
|
||||||
struct clk *clk;
|
struct clk *clk;
|
||||||
|
|
||||||
seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
|
scsr = at91_pmc_read(AT91_PMC_SCSR);
|
||||||
seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
|
pcsr = at91_pmc_read(AT91_PMC_PCSR);
|
||||||
seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
|
sr = at91_pmc_read(AT91_PMC_SR);
|
||||||
seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
|
seq_printf(s, "SCSR = %8x\n", scsr);
|
||||||
seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
|
seq_printf(s, "PCSR = %8x\n", pcsr);
|
||||||
|
seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
|
||||||
|
seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
|
||||||
|
seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
|
||||||
if (cpu_has_pllb())
|
if (cpu_has_pllb())
|
||||||
seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
|
seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
|
||||||
if (cpu_has_utmi())
|
if (cpu_has_utmi()) {
|
||||||
seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
|
uckr = at91_pmc_read(AT91_CKGR_UCKR);
|
||||||
seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
|
seq_printf(s, "UCKR = %8x\n", uckr);
|
||||||
|
}
|
||||||
|
seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
|
||||||
if (cpu_has_upll())
|
if (cpu_has_upll())
|
||||||
seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB));
|
seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
|
||||||
seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
|
seq_printf(s, "SR = %8x\n", sr);
|
||||||
|
|
||||||
seq_printf(s, "\n");
|
seq_printf(s, "\n");
|
||||||
|
|
||||||
|
@ -596,16 +638,14 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
|
||||||
if (cpu_is_at91rm9200()) {
|
if (cpu_is_at91rm9200()) {
|
||||||
uhpck.pmc_mask = AT91RM9200_PMC_UHP;
|
uhpck.pmc_mask = AT91RM9200_PMC_UHP;
|
||||||
udpck.pmc_mask = AT91RM9200_PMC_UDP;
|
udpck.pmc_mask = AT91RM9200_PMC_UDP;
|
||||||
at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
|
at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
|
||||||
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
|
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
|
||||||
cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
|
cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
|
||||||
cpu_is_at91sam9g10()) {
|
cpu_is_at91sam9g10()) {
|
||||||
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
|
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
|
||||||
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
|
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
|
||||||
} else if (cpu_is_at91cap9()) {
|
|
||||||
uhpck.pmc_mask = AT91CAP9_PMC_UHP;
|
|
||||||
}
|
}
|
||||||
at91_sys_write(AT91_CKGR_PLLBR, 0);
|
at91_pmc_write(AT91_CKGR_PLLBR, 0);
|
||||||
|
|
||||||
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
|
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
|
||||||
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
|
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
|
||||||
|
@ -622,13 +662,13 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
|
||||||
/* Setup divider by 10 to reach 48 MHz */
|
/* Setup divider by 10 to reach 48 MHz */
|
||||||
usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
|
usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
|
||||||
|
|
||||||
at91_sys_write(AT91_PMC_USB, usbr);
|
at91_pmc_write(AT91_PMC_USB, usbr);
|
||||||
|
|
||||||
/* Now set uhpck values */
|
/* Now set uhpck values */
|
||||||
uhpck.parent = &utmi_clk;
|
uhpck.parent = &utmi_clk;
|
||||||
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
|
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
|
||||||
uhpck.rate_hz = utmi_clk.rate_hz;
|
uhpck.rate_hz = utmi_clk.rate_hz;
|
||||||
uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
|
uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
|
||||||
}
|
}
|
||||||
|
|
||||||
int __init at91_clock_init(unsigned long main_clock)
|
int __init at91_clock_init(unsigned long main_clock)
|
||||||
|
@ -637,6 +677,10 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||||
int i;
|
int i;
|
||||||
int pll_overclock = false;
|
int pll_overclock = false;
|
||||||
|
|
||||||
|
at91_pmc_base = ioremap(AT91_PMC, 256);
|
||||||
|
if (!at91_pmc_base)
|
||||||
|
panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* When the bootloader initialized the main oscillator correctly,
|
* When the bootloader initialized the main oscillator correctly,
|
||||||
* there's no problem using the cycle counter. But if it didn't,
|
* there's no problem using the cycle counter. But if it didn't,
|
||||||
|
@ -645,14 +689,14 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||||
*/
|
*/
|
||||||
if (!main_clock) {
|
if (!main_clock) {
|
||||||
do {
|
do {
|
||||||
tmp = at91_sys_read(AT91_CKGR_MCFR);
|
tmp = at91_pmc_read(AT91_CKGR_MCFR);
|
||||||
} while (!(tmp & AT91_PMC_MAINRDY));
|
} while (!(tmp & AT91_PMC_MAINRDY));
|
||||||
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
|
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
|
||||||
}
|
}
|
||||||
main_clk.rate_hz = main_clock;
|
main_clk.rate_hz = main_clock;
|
||||||
|
|
||||||
/* report if PLLA is more than mildly overclocked */
|
/* report if PLLA is more than mildly overclocked */
|
||||||
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
|
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
|
||||||
if (cpu_has_300M_plla()) {
|
if (cpu_has_300M_plla()) {
|
||||||
if (plla.rate_hz > 300000000)
|
if (plla.rate_hz > 300000000)
|
||||||
pll_overclock = true;
|
pll_overclock = true;
|
||||||
|
@ -666,8 +710,8 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||||
if (pll_overclock)
|
if (pll_overclock)
|
||||||
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
|
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
|
||||||
|
|
||||||
if (cpu_is_at91sam9g45()) {
|
if (cpu_has_plladiv2()) {
|
||||||
mckr = at91_sys_read(AT91_PMC_MCKR);
|
mckr = at91_pmc_read(AT91_PMC_MCKR);
|
||||||
plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
|
plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -688,6 +732,10 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||||
* (obtain the USB High Speed 480 MHz when input is 12 MHz)
|
* (obtain the USB High Speed 480 MHz when input is 12 MHz)
|
||||||
*/
|
*/
|
||||||
utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
|
utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
|
||||||
|
|
||||||
|
/* UTMI bias and PLL are managed at the same time */
|
||||||
|
if (cpu_has_upll())
|
||||||
|
utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -703,10 +751,10 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||||
* MCK and CPU derive from one of those primary clocks.
|
* MCK and CPU derive from one of those primary clocks.
|
||||||
* For now, assume this parentage won't change.
|
* For now, assume this parentage won't change.
|
||||||
*/
|
*/
|
||||||
mckr = at91_sys_read(AT91_PMC_MCKR);
|
mckr = at91_pmc_read(AT91_PMC_MCKR);
|
||||||
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
|
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
|
||||||
freq = mck.parent->rate_hz;
|
freq = mck.parent->rate_hz;
|
||||||
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
|
freq /= pmc_prescaler_divider(mckr); /* prescale */
|
||||||
if (cpu_is_at91rm9200()) {
|
if (cpu_is_at91rm9200()) {
|
||||||
mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||||
} else if (cpu_is_at91sam9g20()) {
|
} else if (cpu_is_at91sam9g20()) {
|
||||||
|
@ -714,13 +762,19 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||||
freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
|
freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
|
||||||
if (mckr & AT91_PMC_PDIV)
|
if (mckr & AT91_PMC_PDIV)
|
||||||
freq /= 2; /* processor clock division */
|
freq /= 2; /* processor clock division */
|
||||||
} else if (cpu_is_at91sam9g45()) {
|
} else if (cpu_has_mdiv3()) {
|
||||||
mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
|
mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
|
||||||
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||||
} else {
|
} else {
|
||||||
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (cpu_has_alt_prescaler()) {
|
||||||
|
/* Programmable clocks can use MCK */
|
||||||
|
mck.type |= CLK_TYPE_PRIMARY;
|
||||||
|
mck.id = 4;
|
||||||
|
}
|
||||||
|
|
||||||
/* Register the PMC's standard clocks */
|
/* Register the PMC's standard clocks */
|
||||||
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
|
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
|
||||||
at91_clk_add(standard_pmc_clocks[i]);
|
at91_clk_add(standard_pmc_clocks[i]);
|
||||||
|
@ -770,9 +824,15 @@ static int __init at91_clock_reset(void)
|
||||||
pr_debug("Clocks: disable unused %s\n", clk->name);
|
pr_debug("Clocks: disable unused %s\n", clk->name);
|
||||||
}
|
}
|
||||||
|
|
||||||
at91_sys_write(AT91_PMC_PCDR, pcdr);
|
at91_pmc_write(AT91_PMC_PCDR, pcdr);
|
||||||
at91_sys_write(AT91_PMC_SCDR, scdr);
|
at91_pmc_write(AT91_PMC_SCDR, scdr);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
late_initcall(at91_clock_reset);
|
late_initcall(at91_clock_reset);
|
||||||
|
|
||||||
|
void at91sam9_idle(void)
|
||||||
|
{
|
||||||
|
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||||
|
cpu_do_idle();
|
||||||
|
}
|
||||||
|
|
|
@ -39,20 +39,15 @@ static int at91_enter_idle(struct cpuidle_device *dev,
|
||||||
{
|
{
|
||||||
struct timeval before, after;
|
struct timeval before, after;
|
||||||
int idle_time;
|
int idle_time;
|
||||||
u32 saved_lpr;
|
|
||||||
|
|
||||||
local_irq_disable();
|
local_irq_disable();
|
||||||
do_gettimeofday(&before);
|
do_gettimeofday(&before);
|
||||||
if (index == 0)
|
if (index == 0)
|
||||||
/* Wait for interrupt state */
|
/* Wait for interrupt state */
|
||||||
cpu_do_idle();
|
cpu_do_idle();
|
||||||
else if (index == 1) {
|
else if (index == 1)
|
||||||
asm("b 1f; .align 5; 1:");
|
at91_standby();
|
||||||
asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
|
|
||||||
saved_lpr = sdram_selfrefresh_enable();
|
|
||||||
cpu_do_idle();
|
|
||||||
sdram_selfrefresh_disable(saved_lpr);
|
|
||||||
}
|
|
||||||
do_gettimeofday(&after);
|
do_gettimeofday(&after);
|
||||||
local_irq_enable();
|
local_irq_enable();
|
||||||
idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
|
idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
|
||||||
|
|
|
@ -28,6 +28,7 @@ extern void __init at91_aic_init(unsigned int priority[]);
|
||||||
|
|
||||||
/* Timer */
|
/* Timer */
|
||||||
struct sys_timer;
|
struct sys_timer;
|
||||||
|
extern void at91rm9200_ioremap_st(u32 addr);
|
||||||
extern struct sys_timer at91rm9200_timer;
|
extern struct sys_timer at91rm9200_timer;
|
||||||
extern void at91sam926x_ioremap_pit(u32 addr);
|
extern void at91sam926x_ioremap_pit(u32 addr);
|
||||||
extern struct sys_timer at91sam926x_timer;
|
extern struct sys_timer at91sam926x_timer;
|
||||||
|
@ -45,7 +46,6 @@ extern void __init at91sam9261_set_console_clock(int id);
|
||||||
extern void __init at91sam9263_set_console_clock(int id);
|
extern void __init at91sam9263_set_console_clock(int id);
|
||||||
extern void __init at91sam9rl_set_console_clock(int id);
|
extern void __init at91sam9rl_set_console_clock(int id);
|
||||||
extern void __init at91sam9g45_set_console_clock(int id);
|
extern void __init at91sam9g45_set_console_clock(int id);
|
||||||
extern void __init at91cap9_set_console_clock(int id);
|
|
||||||
#ifdef CONFIG_AT91_PMC_UNIT
|
#ifdef CONFIG_AT91_PMC_UNIT
|
||||||
extern int __init at91_clock_init(unsigned long main_clock);
|
extern int __init at91_clock_init(unsigned long main_clock);
|
||||||
#else
|
#else
|
||||||
|
@ -57,6 +57,9 @@ struct device;
|
||||||
extern void at91_irq_suspend(void);
|
extern void at91_irq_suspend(void);
|
||||||
extern void at91_irq_resume(void);
|
extern void at91_irq_resume(void);
|
||||||
|
|
||||||
|
/* idle */
|
||||||
|
extern void at91sam9_idle(void);
|
||||||
|
|
||||||
/* reset */
|
/* reset */
|
||||||
extern void at91_ioremap_rstc(u32 base_addr);
|
extern void at91_ioremap_rstc(u32 base_addr);
|
||||||
extern void at91sam9_alt_restart(char, const char *);
|
extern void at91sam9_alt_restart(char, const char *);
|
||||||
|
@ -65,6 +68,12 @@ extern void at91sam9g45_restart(char, const char *);
|
||||||
/* shutdown */
|
/* shutdown */
|
||||||
extern void at91_ioremap_shdwc(u32 base_addr);
|
extern void at91_ioremap_shdwc(u32 base_addr);
|
||||||
|
|
||||||
|
/* Matrix */
|
||||||
|
extern void at91_ioremap_matrix(u32 base_addr);
|
||||||
|
|
||||||
|
/* Ram Controler */
|
||||||
|
extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
|
||||||
|
|
||||||
/* GPIO */
|
/* GPIO */
|
||||||
#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
|
#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
|
||||||
#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
|
#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
|
||||||
|
|
23
arch/arm/mach-at91/include/mach/at91_matrix.h
Normal file
23
arch/arm/mach-at91/include/mach/at91_matrix.h
Normal file
|
@ -0,0 +1,23 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||||
|
*
|
||||||
|
* Under GPLv2
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __MACH_AT91_MATRIX_H__
|
||||||
|
#define __MACH_AT91_MATRIX_H__
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
extern void __iomem *at91_matrix_base;
|
||||||
|
|
||||||
|
#define at91_matrix_read(field) \
|
||||||
|
__raw_readl(at91_matrix_base + field)
|
||||||
|
|
||||||
|
#define at91_matrix_write(field, value) \
|
||||||
|
__raw_writel(value, at91_matrix_base + field);
|
||||||
|
|
||||||
|
#else
|
||||||
|
.extern at91_matrix_base
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __MACH_AT91_MATRIX_H__ */
|
|
@ -16,17 +16,27 @@
|
||||||
#ifndef AT91_PMC_H
|
#ifndef AT91_PMC_H
|
||||||
#define AT91_PMC_H
|
#define AT91_PMC_H
|
||||||
|
|
||||||
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
|
#ifndef __ASSEMBLY__
|
||||||
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
|
extern void __iomem *at91_pmc_base;
|
||||||
|
|
||||||
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
|
#define at91_pmc_read(field) \
|
||||||
|
__raw_readl(at91_pmc_base + field)
|
||||||
|
|
||||||
|
#define at91_pmc_write(field, value) \
|
||||||
|
__raw_writel(value, at91_pmc_base + field)
|
||||||
|
#else
|
||||||
|
.extern at91_aic_base
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
|
||||||
|
#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
|
||||||
|
|
||||||
|
#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
|
||||||
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
|
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
|
||||||
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
|
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
|
||||||
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
|
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
|
||||||
#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */
|
|
||||||
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
|
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
|
||||||
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
|
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
|
||||||
#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
|
|
||||||
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
|
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
|
||||||
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
|
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
|
||||||
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
|
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
|
||||||
|
@ -36,27 +46,31 @@
|
||||||
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
|
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
|
||||||
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
|
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
|
||||||
|
|
||||||
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
|
#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
|
||||||
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
|
#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
|
||||||
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
|
#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
|
||||||
|
|
||||||
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */
|
#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
|
||||||
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
|
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
|
||||||
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
|
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
|
||||||
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
|
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
|
||||||
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
|
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
|
||||||
|
|
||||||
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
|
#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
|
||||||
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
||||||
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
|
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
|
||||||
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
|
||||||
|
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
||||||
|
#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
|
||||||
|
#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
|
||||||
|
#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
|
||||||
|
|
||||||
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
|
#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
|
||||||
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
|
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
|
||||||
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
|
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
|
||||||
|
|
||||||
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
|
#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
|
||||||
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
|
#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
|
||||||
#define AT91_PMC_DIV (0xff << 0) /* Divider */
|
#define AT91_PMC_DIV (0xff << 0) /* Divider */
|
||||||
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
|
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
|
||||||
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
|
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
|
||||||
|
@ -67,27 +81,37 @@
|
||||||
#define AT91_PMC_USBDIV_4 (2 << 28)
|
#define AT91_PMC_USBDIV_4 (2 << 28)
|
||||||
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
|
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
|
||||||
|
|
||||||
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
|
#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
|
||||||
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
|
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
|
||||||
#define AT91_PMC_CSS_SLOW (0 << 0)
|
#define AT91_PMC_CSS_SLOW (0 << 0)
|
||||||
#define AT91_PMC_CSS_MAIN (1 << 0)
|
#define AT91_PMC_CSS_MAIN (1 << 0)
|
||||||
#define AT91_PMC_CSS_PLLA (2 << 0)
|
#define AT91_PMC_CSS_PLLA (2 << 0)
|
||||||
#define AT91_PMC_CSS_PLLB (3 << 0)
|
#define AT91_PMC_CSS_PLLB (3 << 0)
|
||||||
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
|
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
|
||||||
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
|
#define PMC_PRES_OFFSET 2
|
||||||
#define AT91_PMC_PRES_1 (0 << 2)
|
#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
|
||||||
#define AT91_PMC_PRES_2 (1 << 2)
|
#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET)
|
||||||
#define AT91_PMC_PRES_4 (2 << 2)
|
#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET)
|
||||||
#define AT91_PMC_PRES_8 (3 << 2)
|
#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET)
|
||||||
#define AT91_PMC_PRES_16 (4 << 2)
|
#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET)
|
||||||
#define AT91_PMC_PRES_32 (5 << 2)
|
#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET)
|
||||||
#define AT91_PMC_PRES_64 (6 << 2)
|
#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET)
|
||||||
|
#define PMC_ALT_PRES_OFFSET 4
|
||||||
|
#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */
|
||||||
|
#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET)
|
||||||
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
|
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
|
||||||
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
|
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
|
||||||
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
|
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
|
||||||
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
|
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
|
||||||
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
|
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
|
||||||
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
|
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
|
||||||
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
|
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
|
||||||
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
|
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
|
||||||
#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
|
#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
|
||||||
|
@ -99,35 +123,55 @@
|
||||||
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
|
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
|
||||||
#define AT91_PMC_PLLADIV2_ON (1 << 12)
|
#define AT91_PMC_PLLADIV2_ON (1 << 12)
|
||||||
|
|
||||||
#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */
|
#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
|
||||||
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
|
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
|
||||||
#define AT91_PMC_USBS_PLLA (0 << 0)
|
#define AT91_PMC_USBS_PLLA (0 << 0)
|
||||||
#define AT91_PMC_USBS_UPLL (1 << 0)
|
#define AT91_PMC_USBS_UPLL (1 << 0)
|
||||||
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
|
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
|
||||||
|
|
||||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
|
#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
|
||||||
|
#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
|
||||||
|
#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
|
||||||
|
#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
|
||||||
|
|
||||||
|
#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
|
||||||
|
#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
|
||||||
|
#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
|
||||||
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
|
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
|
||||||
#define AT91_PMC_CSSMCK_CSS (0 << 8)
|
#define AT91_PMC_CSSMCK_CSS (0 << 8)
|
||||||
#define AT91_PMC_CSSMCK_MCK (1 << 8)
|
#define AT91_PMC_CSSMCK_MCK (1 << 8)
|
||||||
|
|
||||||
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
|
#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
|
||||||
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
|
#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
|
||||||
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
|
#define AT91_PMC_SR 0x68 /* Status Register */
|
||||||
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
|
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
|
||||||
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
||||||
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
||||||
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
|
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
|
||||||
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */
|
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */
|
||||||
#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
|
|
||||||
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
|
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
|
||||||
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
||||||
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
||||||
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
||||||
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
|
||||||
|
#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
|
||||||
|
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
|
||||||
|
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
|
||||||
|
|
||||||
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
|
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
|
||||||
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
|
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
|
||||||
|
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
|
||||||
|
#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
|
||||||
|
|
||||||
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
|
#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */
|
||||||
|
#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
|
||||||
|
#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
|
||||||
|
|
||||||
|
#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */
|
||||||
|
#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
|
||||||
|
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */
|
||||||
|
#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */
|
||||||
|
#define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV)
|
||||||
|
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
32
arch/arm/mach-at91/include/mach/at91_ramc.h
Normal file
32
arch/arm/mach-at91/include/mach/at91_ramc.h
Normal file
|
@ -0,0 +1,32 @@
|
||||||
|
/*
|
||||||
|
* Header file for the Atmel RAM Controller
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||||
|
*
|
||||||
|
* Under GPLv2 only
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __AT91_RAMC_H__
|
||||||
|
#define __AT91_RAMC_H__
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
extern void __iomem *at91_ramc_base[];
|
||||||
|
|
||||||
|
#define at91_ramc_read(id, field) \
|
||||||
|
__raw_readl(at91_ramc_base[id] + field)
|
||||||
|
|
||||||
|
#define at91_ramc_write(id, field, value) \
|
||||||
|
__raw_writel(value, at91_ramc_base[id] + field)
|
||||||
|
#else
|
||||||
|
.extern at91_ramc_base
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define AT91_MEMCTRL_MC 0
|
||||||
|
#define AT91_MEMCTRL_SDRAMC 1
|
||||||
|
#define AT91_MEMCTRL_DDRSDR 2
|
||||||
|
|
||||||
|
#include <mach/at91rm9200_sdramc.h>
|
||||||
|
#include <mach/at91sam9_ddrsdr.h>
|
||||||
|
#include <mach/at91sam9_sdramc.h>
|
||||||
|
|
||||||
|
#endif /* __AT91_RAMC_H__ */
|
|
@ -16,34 +16,46 @@
|
||||||
#ifndef AT91_ST_H
|
#ifndef AT91_ST_H
|
||||||
#define AT91_ST_H
|
#define AT91_ST_H
|
||||||
|
|
||||||
#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
|
#ifndef __ASSEMBLY__
|
||||||
|
extern void __iomem *at91_st_base;
|
||||||
|
|
||||||
|
#define at91_st_read(field) \
|
||||||
|
__raw_readl(at91_st_base + field)
|
||||||
|
|
||||||
|
#define at91_st_write(field, value) \
|
||||||
|
__raw_writel(value, at91_st_base + field);
|
||||||
|
#else
|
||||||
|
.extern at91_st_base
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define AT91_ST_CR 0x00 /* Control Register */
|
||||||
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
|
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
|
||||||
|
|
||||||
#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
|
#define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
|
||||||
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
|
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
|
||||||
|
|
||||||
#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
|
#define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
|
||||||
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
|
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
|
||||||
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
|
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
|
||||||
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
|
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
|
||||||
|
|
||||||
#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
|
#define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
|
||||||
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
|
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
|
||||||
|
|
||||||
#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
|
#define AT91_ST_SR 0x10 /* Status Register */
|
||||||
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
|
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
|
||||||
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
|
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
|
||||||
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
|
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
|
||||||
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
|
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
|
||||||
|
|
||||||
#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
|
#define AT91_ST_IER 0x14 /* Interrupt Enable Register */
|
||||||
#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
|
#define AT91_ST_IDR 0x18 /* Interrupt Disable Register */
|
||||||
#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
|
#define AT91_ST_IMR 0x1c /* Interrupt Mask Register */
|
||||||
|
|
||||||
#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
|
#define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */
|
||||||
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
|
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
|
||||||
|
|
||||||
#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
|
#define AT91_ST_CRTR 0x24 /* Current Real-time Register */
|
||||||
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
|
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -1,122 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-at91/include/mach/at91cap9.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Atmel Corporation.
|
|
||||||
*
|
|
||||||
* Common definitions.
|
|
||||||
* Based on AT91CAP9 datasheet revision B (Preliminary).
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef AT91CAP9_H
|
|
||||||
#define AT91CAP9_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Peripheral identifiers/interrupts.
|
|
||||||
*/
|
|
||||||
#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
|
|
||||||
#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
|
|
||||||
#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
|
|
||||||
#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
|
|
||||||
#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
|
|
||||||
#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
|
|
||||||
#define AT91CAP9_ID_US0 8 /* USART 0 */
|
|
||||||
#define AT91CAP9_ID_US1 9 /* USART 1 */
|
|
||||||
#define AT91CAP9_ID_US2 10 /* USART 2 */
|
|
||||||
#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
|
|
||||||
#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
|
|
||||||
#define AT91CAP9_ID_CAN 13 /* CAN */
|
|
||||||
#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
|
|
||||||
#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
|
|
||||||
#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
|
|
||||||
#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
|
|
||||||
#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
|
|
||||||
#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
|
|
||||||
#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
|
|
||||||
#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
|
|
||||||
#define AT91CAP9_ID_EMAC 22 /* Ethernet */
|
|
||||||
#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
|
|
||||||
#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
|
|
||||||
#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
|
|
||||||
#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
|
|
||||||
#define AT91CAP9_ID_DMA 27 /* DMA Controller */
|
|
||||||
#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
|
|
||||||
#define AT91CAP9_ID_UHP 29 /* USB Host Port */
|
|
||||||
#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
|
|
||||||
#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* User Peripheral physical base addresses.
|
|
||||||
*/
|
|
||||||
#define AT91CAP9_BASE_UDPHS 0xfff78000
|
|
||||||
#define AT91CAP9_BASE_TCB0 0xfff7c000
|
|
||||||
#define AT91CAP9_BASE_TC0 0xfff7c000
|
|
||||||
#define AT91CAP9_BASE_TC1 0xfff7c040
|
|
||||||
#define AT91CAP9_BASE_TC2 0xfff7c080
|
|
||||||
#define AT91CAP9_BASE_MCI0 0xfff80000
|
|
||||||
#define AT91CAP9_BASE_MCI1 0xfff84000
|
|
||||||
#define AT91CAP9_BASE_TWI 0xfff88000
|
|
||||||
#define AT91CAP9_BASE_US0 0xfff8c000
|
|
||||||
#define AT91CAP9_BASE_US1 0xfff90000
|
|
||||||
#define AT91CAP9_BASE_US2 0xfff94000
|
|
||||||
#define AT91CAP9_BASE_SSC0 0xfff98000
|
|
||||||
#define AT91CAP9_BASE_SSC1 0xfff9c000
|
|
||||||
#define AT91CAP9_BASE_AC97C 0xfffa0000
|
|
||||||
#define AT91CAP9_BASE_SPI0 0xfffa4000
|
|
||||||
#define AT91CAP9_BASE_SPI1 0xfffa8000
|
|
||||||
#define AT91CAP9_BASE_CAN 0xfffac000
|
|
||||||
#define AT91CAP9_BASE_PWMC 0xfffb8000
|
|
||||||
#define AT91CAP9_BASE_EMAC 0xfffbc000
|
|
||||||
#define AT91CAP9_BASE_ADC 0xfffc0000
|
|
||||||
#define AT91CAP9_BASE_ISI 0xfffc4000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* System Peripherals (offset from AT91_BASE_SYS)
|
|
||||||
*/
|
|
||||||
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
|
|
||||||
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
|
|
||||||
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
|
|
||||||
(0xfffffd50 - AT91_BASE_SYS) : \
|
|
||||||
(0xfffffd60 - AT91_BASE_SYS))
|
|
||||||
|
|
||||||
#define AT91CAP9_BASE_ECC 0xffffe200
|
|
||||||
#define AT91CAP9_BASE_DMA 0xffffec00
|
|
||||||
#define AT91CAP9_BASE_SMC 0xffffe800
|
|
||||||
#define AT91CAP9_BASE_DBGU AT91_BASE_DBGU1
|
|
||||||
#define AT91CAP9_BASE_PIOA 0xfffff200
|
|
||||||
#define AT91CAP9_BASE_PIOB 0xfffff400
|
|
||||||
#define AT91CAP9_BASE_PIOC 0xfffff600
|
|
||||||
#define AT91CAP9_BASE_PIOD 0xfffff800
|
|
||||||
#define AT91CAP9_BASE_RSTC 0xfffffd00
|
|
||||||
#define AT91CAP9_BASE_SHDWC 0xfffffd10
|
|
||||||
#define AT91CAP9_BASE_RTT 0xfffffd20
|
|
||||||
#define AT91CAP9_BASE_PIT 0xfffffd30
|
|
||||||
#define AT91CAP9_BASE_WDT 0xfffffd40
|
|
||||||
|
|
||||||
#define AT91_USART0 AT91CAP9_BASE_US0
|
|
||||||
#define AT91_USART1 AT91CAP9_BASE_US1
|
|
||||||
#define AT91_USART2 AT91CAP9_BASE_US2
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Internal Memory.
|
|
||||||
*/
|
|
||||||
#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
|
|
||||||
#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
|
|
||||||
|
|
||||||
#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
|
|
||||||
#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
|
|
||||||
|
|
||||||
#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
|
|
||||||
#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
|
|
||||||
#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -1,137 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-at91/include/mach/at91cap9_matrix.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
|
|
||||||
* Copyright (C) 2006 Atmel Corporation.
|
|
||||||
*
|
|
||||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
|
||||||
* Based on AT91CAP9 datasheet revision B (Preliminary).
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef AT91CAP9_MATRIX_H
|
|
||||||
#define AT91CAP9_MATRIX_H
|
|
||||||
|
|
||||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
|
||||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
|
||||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
|
||||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
|
||||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
|
||||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
|
||||||
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
|
|
||||||
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
|
|
||||||
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
|
|
||||||
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
|
|
||||||
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
|
|
||||||
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
|
|
||||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
|
||||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
|
||||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
|
||||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
|
||||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
|
||||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
|
||||||
|
|
||||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
|
||||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
|
||||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
|
||||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
|
||||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
|
||||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
|
||||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
|
|
||||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
|
|
||||||
#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
|
|
||||||
#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
|
|
||||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
|
||||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
|
||||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
|
||||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
|
||||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
|
||||||
|
|
||||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
|
||||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
|
|
||||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
|
||||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
|
|
||||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
|
||||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
|
|
||||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
|
||||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
|
|
||||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
|
||||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
|
|
||||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
|
||||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
|
|
||||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
|
|
||||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
|
|
||||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
|
|
||||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
|
|
||||||
#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
|
|
||||||
#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
|
|
||||||
#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
|
|
||||||
#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
|
|
||||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
|
||||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
|
||||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
|
||||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
|
||||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
|
||||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
|
||||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
|
||||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
|
||||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
|
||||||
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
|
|
||||||
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
|
|
||||||
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
|
|
||||||
|
|
||||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
|
||||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
|
||||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
|
||||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
|
||||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
|
||||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
|
||||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
|
||||||
#define AT91_MATRIX_RCB6 (1 << 6)
|
|
||||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
|
||||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
|
||||||
#define AT91_MATRIX_RCB9 (1 << 9)
|
|
||||||
#define AT91_MATRIX_RCB10 (1 << 10)
|
|
||||||
#define AT91_MATRIX_RCB11 (1 << 11)
|
|
||||||
|
|
||||||
#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
|
|
||||||
#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
|
|
||||||
|
|
||||||
#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */
|
|
||||||
#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */
|
|
||||||
#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */
|
|
||||||
#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */
|
|
||||||
|
|
||||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
|
|
||||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
|
||||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
|
||||||
#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
|
|
||||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
|
||||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
|
||||||
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
|
|
||||||
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
|
||||||
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
|
|
||||||
#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
|
|
||||||
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
|
||||||
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
|
|
||||||
#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
|
|
||||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
|
||||||
#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
|
|
||||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
|
||||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
|
||||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
|
||||||
|
|
||||||
#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
|
|
||||||
#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
|
|
||||||
#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -77,26 +77,22 @@
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* System Peripherals (offset from AT91_BASE_SYS)
|
* System Peripherals
|
||||||
*/
|
*/
|
||||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
|
|
||||||
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
|
|
||||||
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
|
|
||||||
|
|
||||||
#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
|
#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
|
||||||
#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
|
#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
|
||||||
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
|
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
|
||||||
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
|
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
|
||||||
#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
|
#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
|
||||||
|
#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
|
||||||
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
|
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
|
||||||
|
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
|
||||||
|
|
||||||
#define AT91_USART0 AT91RM9200_BASE_US0
|
#define AT91_USART0 AT91RM9200_BASE_US0
|
||||||
#define AT91_USART1 AT91RM9200_BASE_US1
|
#define AT91_USART1 AT91RM9200_BASE_US1
|
||||||
#define AT91_USART2 AT91RM9200_BASE_US2
|
#define AT91_USART2 AT91RM9200_BASE_US2
|
||||||
#define AT91_USART3 AT91RM9200_BASE_US3
|
#define AT91_USART3 AT91RM9200_BASE_US3
|
||||||
|
|
||||||
#define AT91_MATRIX 0 /* not supported */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Internal Memory.
|
* Internal Memory.
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -17,10 +17,10 @@
|
||||||
#define AT91RM9200_MC_H
|
#define AT91RM9200_MC_H
|
||||||
|
|
||||||
/* Memory Controller */
|
/* Memory Controller */
|
||||||
#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
|
#define AT91_MC_RCR 0x00 /* MC Remap Control Register */
|
||||||
#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
|
#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
|
||||||
|
|
||||||
#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
|
#define AT91_MC_ASR 0x04 /* MC Abort Status Register */
|
||||||
#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
|
#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
|
||||||
#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
|
#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
|
||||||
#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
|
#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
|
||||||
|
@ -40,16 +40,16 @@
|
||||||
#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
|
#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
|
||||||
#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
|
#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
|
||||||
|
|
||||||
#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
|
#define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */
|
||||||
|
|
||||||
#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
|
#define AT91_MC_MPR 0x0c /* MC Master Priority Register */
|
||||||
#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
|
#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
|
||||||
#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
|
#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
|
||||||
#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
|
#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
|
||||||
#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
|
#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
|
||||||
|
|
||||||
/* External Bus Interface (EBI) registers */
|
/* External Bus Interface (EBI) registers */
|
||||||
#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
|
#define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */
|
||||||
#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
|
#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
|
||||||
#define AT91_EBI_CS0A_SMC (0 << 0)
|
#define AT91_EBI_CS0A_SMC (0 << 0)
|
||||||
#define AT91_EBI_CS0A_BFC (1 << 0)
|
#define AT91_EBI_CS0A_BFC (1 << 0)
|
||||||
|
@ -66,7 +66,7 @@
|
||||||
#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
|
#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
|
||||||
|
|
||||||
/* Static Memory Controller (SMC) registers */
|
/* Static Memory Controller (SMC) registers */
|
||||||
#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
|
#define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */
|
||||||
#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
|
#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
|
||||||
#define AT91_SMC_NWS_(x) ((x) << 0)
|
#define AT91_SMC_NWS_(x) ((x) << 0)
|
||||||
#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
|
#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
|
||||||
|
@ -87,52 +87,8 @@
|
||||||
#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
|
#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
|
||||||
#define AT91_SMC_RWHOLD_(x) ((x) << 28)
|
#define AT91_SMC_RWHOLD_(x) ((x) << 28)
|
||||||
|
|
||||||
/* SDRAM Controller registers */
|
|
||||||
#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
|
|
||||||
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
|
|
||||||
#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
|
|
||||||
#define AT91_SDRAMC_MODE_NOP (1 << 0)
|
|
||||||
#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
|
|
||||||
#define AT91_SDRAMC_MODE_LMR (3 << 0)
|
|
||||||
#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
|
|
||||||
#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
|
|
||||||
#define AT91_SDRAMC_DBW_32 (0 << 4)
|
|
||||||
#define AT91_SDRAMC_DBW_16 (1 << 4)
|
|
||||||
|
|
||||||
#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
|
|
||||||
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
|
|
||||||
|
|
||||||
#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
|
|
||||||
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
|
|
||||||
#define AT91_SDRAMC_NC_8 (0 << 0)
|
|
||||||
#define AT91_SDRAMC_NC_9 (1 << 0)
|
|
||||||
#define AT91_SDRAMC_NC_10 (2 << 0)
|
|
||||||
#define AT91_SDRAMC_NC_11 (3 << 0)
|
|
||||||
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
|
|
||||||
#define AT91_SDRAMC_NR_11 (0 << 2)
|
|
||||||
#define AT91_SDRAMC_NR_12 (1 << 2)
|
|
||||||
#define AT91_SDRAMC_NR_13 (2 << 2)
|
|
||||||
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
|
|
||||||
#define AT91_SDRAMC_NB_2 (0 << 4)
|
|
||||||
#define AT91_SDRAMC_NB_4 (1 << 4)
|
|
||||||
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
|
|
||||||
#define AT91_SDRAMC_CAS_2 (2 << 5)
|
|
||||||
#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
|
|
||||||
#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
|
|
||||||
#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
|
|
||||||
#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
|
|
||||||
#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
|
|
||||||
#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
|
|
||||||
|
|
||||||
#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
|
|
||||||
#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
|
|
||||||
#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
|
|
||||||
#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
|
|
||||||
#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
|
|
||||||
#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
|
|
||||||
|
|
||||||
/* Burst Flash Controller register */
|
/* Burst Flash Controller register */
|
||||||
#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
|
#define AT91_BFC_MR 0xc0 /* Mode Register */
|
||||||
#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
|
#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
|
||||||
#define AT91_BFC_BFCOM_DISABLED (0 << 0)
|
#define AT91_BFC_BFCOM_DISABLED (0 << 0)
|
||||||
#define AT91_BFC_BFCOM_ASYNC (1 << 0)
|
#define AT91_BFC_BFCOM_ASYNC (1 << 0)
|
||||||
|
|
63
arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
Normal file
63
arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
Normal file
|
@ -0,0 +1,63 @@
|
||||||
|
/*
|
||||||
|
* arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2005 Ivan Kokshaysky
|
||||||
|
* Copyright (C) SAN People
|
||||||
|
*
|
||||||
|
* Memory Controllers (SDRAMC only) - System peripherals registers.
|
||||||
|
* Based on AT91RM9200 datasheet revision E.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef AT91RM9200_SDRAMC_H
|
||||||
|
#define AT91RM9200_SDRAMC_H
|
||||||
|
|
||||||
|
/* SDRAM Controller registers */
|
||||||
|
#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
|
||||||
|
#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
|
||||||
|
#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
|
||||||
|
#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
|
||||||
|
#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
|
||||||
|
#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
|
||||||
|
#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
|
||||||
|
#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
|
||||||
|
#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
|
||||||
|
#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
|
||||||
|
|
||||||
|
#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
|
||||||
|
#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
|
||||||
|
|
||||||
|
#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
|
||||||
|
#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
|
||||||
|
#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
|
||||||
|
#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
|
||||||
|
#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
|
||||||
|
#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
|
||||||
|
#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
|
||||||
|
#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
|
||||||
|
#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
|
||||||
|
#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
|
||||||
|
#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
|
||||||
|
#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
|
||||||
|
#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
|
||||||
|
#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
|
||||||
|
#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
|
||||||
|
#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
|
||||||
|
#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
|
||||||
|
#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
|
||||||
|
#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
|
||||||
|
#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
|
||||||
|
#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
|
||||||
|
|
||||||
|
#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
|
||||||
|
#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
|
||||||
|
#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
|
||||||
|
#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
|
||||||
|
#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
|
||||||
|
#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
|
||||||
|
|
||||||
|
#endif
|
|
@ -78,15 +78,12 @@
|
||||||
#define AT91SAM9260_BASE_ADC 0xfffe0000
|
#define AT91SAM9260_BASE_ADC 0xfffe0000
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* System Peripherals (offset from AT91_BASE_SYS)
|
* System Peripherals
|
||||||
*/
|
*/
|
||||||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
|
||||||
|
|
||||||
#define AT91SAM9260_BASE_ECC 0xffffe800
|
#define AT91SAM9260_BASE_ECC 0xffffe800
|
||||||
|
#define AT91SAM9260_BASE_SDRAMC 0xffffea00
|
||||||
#define AT91SAM9260_BASE_SMC 0xffffec00
|
#define AT91SAM9260_BASE_SMC 0xffffec00
|
||||||
|
#define AT91SAM9260_BASE_MATRIX 0xffffee00
|
||||||
#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
|
#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
|
||||||
#define AT91SAM9260_BASE_PIOA 0xfffff400
|
#define AT91SAM9260_BASE_PIOA 0xfffff400
|
||||||
#define AT91SAM9260_BASE_PIOB 0xfffff600
|
#define AT91SAM9260_BASE_PIOB 0xfffff600
|
||||||
|
@ -96,6 +93,7 @@
|
||||||
#define AT91SAM9260_BASE_RTT 0xfffffd20
|
#define AT91SAM9260_BASE_RTT 0xfffffd20
|
||||||
#define AT91SAM9260_BASE_PIT 0xfffffd30
|
#define AT91SAM9260_BASE_PIT 0xfffffd30
|
||||||
#define AT91SAM9260_BASE_WDT 0xfffffd40
|
#define AT91SAM9260_BASE_WDT 0xfffffd40
|
||||||
|
#define AT91SAM9260_BASE_GPBR 0xfffffd50
|
||||||
|
|
||||||
#define AT91_USART0 AT91SAM9260_BASE_US0
|
#define AT91_USART0 AT91SAM9260_BASE_US0
|
||||||
#define AT91_USART1 AT91SAM9260_BASE_US1
|
#define AT91_USART1 AT91SAM9260_BASE_US1
|
||||||
|
@ -115,6 +113,8 @@
|
||||||
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
|
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
|
||||||
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
|
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
|
||||||
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
|
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
|
||||||
|
#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */
|
||||||
|
#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */
|
||||||
|
|
||||||
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
|
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
|
||||||
|
|
||||||
|
@ -128,6 +128,8 @@
|
||||||
#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
|
#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
|
||||||
#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
|
#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
|
||||||
#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
|
#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
|
||||||
|
#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */
|
||||||
|
#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
|
||||||
|
|
||||||
#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
|
#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
|
||||||
|
|
||||||
|
|
|
@ -15,12 +15,12 @@
|
||||||
#ifndef AT91SAM9260_MATRIX_H
|
#ifndef AT91SAM9260_MATRIX_H
|
||||||
#define AT91SAM9260_MATRIX_H
|
#define AT91SAM9260_MATRIX_H
|
||||||
|
|
||||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||||
|
@ -28,11 +28,11 @@
|
||||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||||
|
|
||||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||||
|
@ -43,11 +43,11 @@
|
||||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||||
|
|
||||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||||
|
@ -55,11 +55,11 @@
|
||||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||||
|
|
||||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||||
|
|
||||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
|
#define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */
|
||||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||||
|
|
|
@ -63,14 +63,11 @@
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* System Peripherals (offset from AT91_BASE_SYS)
|
* System Peripherals
|
||||||
*/
|
*/
|
||||||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
|
||||||
|
|
||||||
#define AT91SAM9261_BASE_SMC 0xffffec00
|
#define AT91SAM9261_BASE_SMC 0xffffec00
|
||||||
|
#define AT91SAM9261_BASE_MATRIX 0xffffee00
|
||||||
|
#define AT91SAM9261_BASE_SDRAMC 0xffffea00
|
||||||
#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
|
#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
|
||||||
#define AT91SAM9261_BASE_PIOA 0xfffff400
|
#define AT91SAM9261_BASE_PIOA 0xfffff400
|
||||||
#define AT91SAM9261_BASE_PIOB 0xfffff600
|
#define AT91SAM9261_BASE_PIOB 0xfffff600
|
||||||
|
@ -80,6 +77,7 @@
|
||||||
#define AT91SAM9261_BASE_RTT 0xfffffd20
|
#define AT91SAM9261_BASE_RTT 0xfffffd20
|
||||||
#define AT91SAM9261_BASE_PIT 0xfffffd30
|
#define AT91SAM9261_BASE_PIT 0xfffffd30
|
||||||
#define AT91SAM9261_BASE_WDT 0xfffffd40
|
#define AT91SAM9261_BASE_WDT 0xfffffd40
|
||||||
|
#define AT91SAM9261_BASE_GPBR 0xfffffd50
|
||||||
|
|
||||||
#define AT91_USART0 AT91SAM9261_BASE_US0
|
#define AT91_USART0 AT91SAM9261_BASE_US0
|
||||||
#define AT91_USART1 AT91SAM9261_BASE_US1
|
#define AT91_USART1 AT91SAM9261_BASE_US1
|
||||||
|
|
|
@ -15,15 +15,15 @@
|
||||||
#ifndef AT91SAM9261_MATRIX_H
|
#ifndef AT91SAM9261_MATRIX_H
|
||||||
#define AT91SAM9261_MATRIX_H
|
#define AT91SAM9261_MATRIX_H
|
||||||
|
|
||||||
#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
|
#define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */
|
||||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||||
|
|
||||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
|
#define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */
|
||||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
|
#define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */
|
||||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
|
#define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */
|
||||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
|
#define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */
|
||||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
|
#define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */
|
||||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||||
|
@ -31,7 +31,7 @@
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||||
|
|
||||||
#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
|
#define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */
|
||||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||||
|
@ -43,7 +43,7 @@
|
||||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||||
#define AT91_MATRIX_DTCM_64 (7 << 4)
|
#define AT91_MATRIX_DTCM_64 (7 << 4)
|
||||||
|
|
||||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
|
#define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */
|
||||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||||
|
@ -58,7 +58,7 @@
|
||||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||||
|
|
||||||
#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
|
#define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */
|
||||||
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
|
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -72,18 +72,15 @@
|
||||||
#define AT91SAM9263_BASE_2DGE 0xfffc8000
|
#define AT91SAM9263_BASE_2DGE 0xfffc8000
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* System Peripherals (offset from AT91_BASE_SYS)
|
* System Peripherals
|
||||||
*/
|
*/
|
||||||
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
|
|
||||||
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
|
|
||||||
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
|
||||||
|
|
||||||
#define AT91SAM9263_BASE_ECC0 0xffffe000
|
#define AT91SAM9263_BASE_ECC0 0xffffe000
|
||||||
|
#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
|
||||||
#define AT91SAM9263_BASE_SMC0 0xffffe400
|
#define AT91SAM9263_BASE_SMC0 0xffffe400
|
||||||
#define AT91SAM9263_BASE_ECC1 0xffffe600
|
#define AT91SAM9263_BASE_ECC1 0xffffe600
|
||||||
|
#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
|
||||||
#define AT91SAM9263_BASE_SMC1 0xffffea00
|
#define AT91SAM9263_BASE_SMC1 0xffffea00
|
||||||
|
#define AT91SAM9263_BASE_MATRIX 0xffffec00
|
||||||
#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
|
#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
|
||||||
#define AT91SAM9263_BASE_PIOA 0xfffff200
|
#define AT91SAM9263_BASE_PIOA 0xfffff200
|
||||||
#define AT91SAM9263_BASE_PIOB 0xfffff400
|
#define AT91SAM9263_BASE_PIOB 0xfffff400
|
||||||
|
@ -96,6 +93,7 @@
|
||||||
#define AT91SAM9263_BASE_PIT 0xfffffd30
|
#define AT91SAM9263_BASE_PIT 0xfffffd30
|
||||||
#define AT91SAM9263_BASE_WDT 0xfffffd40
|
#define AT91SAM9263_BASE_WDT 0xfffffd40
|
||||||
#define AT91SAM9263_BASE_RTT1 0xfffffd50
|
#define AT91SAM9263_BASE_RTT1 0xfffffd50
|
||||||
|
#define AT91SAM9263_BASE_GPBR 0xfffffd60
|
||||||
|
|
||||||
#define AT91_USART0 AT91SAM9263_BASE_US0
|
#define AT91_USART0 AT91SAM9263_BASE_US0
|
||||||
#define AT91_USART1 AT91SAM9263_BASE_US1
|
#define AT91_USART1 AT91SAM9263_BASE_US1
|
||||||
|
|
|
@ -15,15 +15,15 @@
|
||||||
#ifndef AT91SAM9263_MATRIX_H
|
#ifndef AT91SAM9263_MATRIX_H
|
||||||
#define AT91SAM9263_MATRIX_H
|
#define AT91SAM9263_MATRIX_H
|
||||||
|
|
||||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||||
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
|
#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
|
||||||
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
|
#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
|
||||||
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
|
#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
|
||||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||||
|
@ -31,14 +31,14 @@
|
||||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||||
|
|
||||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
|
||||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
|
#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
|
||||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
|
#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
|
||||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||||
|
@ -49,22 +49,22 @@
|
||||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||||
|
|
||||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
|
#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
|
||||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
|
#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
|
||||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
|
#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
|
||||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
|
#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
|
||||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
|
#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
|
||||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
|
||||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
|
#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
|
||||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
|
#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
|
||||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
|
#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
|
||||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
|
#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
|
||||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
|
#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
|
||||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||||
|
@ -75,7 +75,7 @@
|
||||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
||||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
||||||
|
|
||||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||||
|
@ -86,7 +86,7 @@
|
||||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
#define AT91_MATRIX_RCB7 (1 << 7)
|
||||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
#define AT91_MATRIX_RCB8 (1 << 8)
|
||||||
|
|
||||||
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
|
#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
|
||||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||||
|
@ -96,7 +96,7 @@
|
||||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||||
|
|
||||||
#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
|
#define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */
|
||||||
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||||
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
|
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
|
||||||
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
|
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
|
||||||
|
@ -114,7 +114,7 @@
|
||||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
|
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
|
||||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
|
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
|
||||||
|
|
||||||
#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
|
#define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */
|
||||||
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||||
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
|
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
|
||||||
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
|
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
|
||||||
|
|
|
@ -59,7 +59,6 @@
|
||||||
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
|
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
|
||||||
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
|
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
|
||||||
#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
|
#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
|
||||||
#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
|
|
||||||
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
|
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
|
||||||
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
|
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
|
||||||
|
|
||||||
|
@ -76,7 +75,6 @@
|
||||||
#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
|
#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
|
||||||
|
|
||||||
#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
|
#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
|
||||||
#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
|
|
||||||
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
|
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
|
||||||
#define AT91_DDRSDRC_LPCB_DISABLE 0
|
#define AT91_DDRSDRC_LPCB_DISABLE 0
|
||||||
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
|
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
|
||||||
|
@ -94,11 +92,9 @@
|
||||||
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
|
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
|
||||||
|
|
||||||
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
|
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
|
||||||
#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
|
|
||||||
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
|
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
|
||||||
#define AT91_DDRSDRC_MD_SDR 0
|
#define AT91_DDRSDRC_MD_SDR 0
|
||||||
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
|
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
|
||||||
#define AT91CAP9_DDRSDRC_MD_DDR 2
|
|
||||||
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
|
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
|
||||||
#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
|
#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
|
||||||
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
|
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
|
||||||
|
@ -106,16 +102,10 @@
|
||||||
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
|
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
|
||||||
|
|
||||||
#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
|
#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
|
||||||
#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
|
|
||||||
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
|
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
|
||||||
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
|
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
|
||||||
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
|
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
|
||||||
#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
|
|
||||||
#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
|
|
||||||
#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
|
|
||||||
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
|
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
|
||||||
#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
|
|
||||||
#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
|
|
||||||
|
|
||||||
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
|
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
|
||||||
#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
|
#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
|
||||||
|
@ -131,10 +121,4 @@
|
||||||
#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
|
#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
|
||||||
#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
|
#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
|
||||||
|
|
||||||
/* Register access macros */
|
|
||||||
#define at91_ramc_read(num, reg) \
|
|
||||||
at91_sys_read(AT91_DDRSDRC##num + reg)
|
|
||||||
#define at91_ramc_write(num, reg, value) \
|
|
||||||
at91_sys_write(AT91_DDRSDRC##num + reg, value)
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -82,10 +82,4 @@
|
||||||
#define AT91_SDRAMC_MD_SDRAM 0
|
#define AT91_SDRAMC_MD_SDRAM 0
|
||||||
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
|
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
|
||||||
|
|
||||||
/* Register access macros */
|
|
||||||
#define at91_ramc_read(num, reg) \
|
|
||||||
at91_sys_read(AT91_SDRAMC##num + reg)
|
|
||||||
#define at91_ramc_write(num, reg, value) \
|
|
||||||
at91_sys_write(AT91_SDRAMC##num + reg, value)
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -84,17 +84,14 @@
|
||||||
#define AT91SAM9G45_BASE_TC5 0xfffd4080
|
#define AT91SAM9G45_BASE_TC5 0xfffd4080
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* System Peripherals (offset from AT91_BASE_SYS)
|
* System Peripherals
|
||||||
*/
|
*/
|
||||||
#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
|
|
||||||
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
|
|
||||||
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
|
||||||
|
|
||||||
#define AT91SAM9G45_BASE_ECC 0xffffe200
|
#define AT91SAM9G45_BASE_ECC 0xffffe200
|
||||||
|
#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
|
||||||
|
#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
|
||||||
#define AT91SAM9G45_BASE_DMA 0xffffec00
|
#define AT91SAM9G45_BASE_DMA 0xffffec00
|
||||||
#define AT91SAM9G45_BASE_SMC 0xffffe800
|
#define AT91SAM9G45_BASE_SMC 0xffffe800
|
||||||
|
#define AT91SAM9G45_BASE_MATRIX 0xffffea00
|
||||||
#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
|
#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
|
||||||
#define AT91SAM9G45_BASE_PIOA 0xfffff200
|
#define AT91SAM9G45_BASE_PIOA 0xfffff200
|
||||||
#define AT91SAM9G45_BASE_PIOB 0xfffff400
|
#define AT91SAM9G45_BASE_PIOB 0xfffff400
|
||||||
|
@ -107,6 +104,7 @@
|
||||||
#define AT91SAM9G45_BASE_PIT 0xfffffd30
|
#define AT91SAM9G45_BASE_PIT 0xfffffd30
|
||||||
#define AT91SAM9G45_BASE_WDT 0xfffffd40
|
#define AT91SAM9G45_BASE_WDT 0xfffffd40
|
||||||
#define AT91SAM9G45_BASE_RTC 0xfffffdb0
|
#define AT91SAM9G45_BASE_RTC 0xfffffdb0
|
||||||
|
#define AT91SAM9G45_BASE_GPBR 0xfffffd60
|
||||||
|
|
||||||
#define AT91_USART0 AT91SAM9G45_BASE_US0
|
#define AT91_USART0 AT91SAM9G45_BASE_US0
|
||||||
#define AT91_USART1 AT91SAM9G45_BASE_US1
|
#define AT91_USART1 AT91SAM9G45_BASE_US1
|
||||||
|
|
|
@ -15,18 +15,18 @@
|
||||||
#ifndef AT91SAM9G45_MATRIX_H
|
#ifndef AT91SAM9G45_MATRIX_H
|
||||||
#define AT91SAM9G45_MATRIX_H
|
#define AT91SAM9G45_MATRIX_H
|
||||||
|
|
||||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||||
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
|
#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
|
||||||
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
|
#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
|
||||||
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
|
#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
|
||||||
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
|
#define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */
|
||||||
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
|
#define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */
|
||||||
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
|
#define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */
|
||||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||||
|
@ -37,14 +37,14 @@
|
||||||
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
|
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
|
||||||
#define AT91_MATRIX_ULBT_128 (7 << 0)
|
#define AT91_MATRIX_ULBT_128 (7 << 0)
|
||||||
|
|
||||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
|
||||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
|
#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
|
||||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
|
#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
|
||||||
#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||||
|
@ -52,22 +52,22 @@
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||||
|
|
||||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
|
#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
|
||||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
|
#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
|
||||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
|
#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
|
||||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
|
#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
|
||||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
|
#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
|
||||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
|
||||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
|
#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
|
||||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
|
#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
|
||||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
|
#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
|
||||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
|
#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
|
||||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
|
#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
|
||||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||||
|
@ -81,7 +81,7 @@
|
||||||
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
|
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
|
||||||
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
|
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
|
||||||
|
|
||||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||||
|
@ -95,7 +95,7 @@
|
||||||
#define AT91_MATRIX_RCB10 (1 << 10)
|
#define AT91_MATRIX_RCB10 (1 << 10)
|
||||||
#define AT91_MATRIX_RCB11 (1 << 11)
|
#define AT91_MATRIX_RCB11 (1 << 11)
|
||||||
|
|
||||||
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */
|
#define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */
|
||||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||||
|
@ -107,12 +107,12 @@
|
||||||
#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
|
#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
|
||||||
#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
|
#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
|
||||||
|
|
||||||
#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */
|
#define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */
|
||||||
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
|
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
|
||||||
#define AT91C_VDEC_SEL_OFF (0 << 0)
|
#define AT91C_VDEC_SEL_OFF (0 << 0)
|
||||||
#define AT91C_VDEC_SEL_ON (1 << 0)
|
#define AT91C_VDEC_SEL_ON (1 << 0)
|
||||||
|
|
||||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */
|
#define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */
|
||||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||||
|
@ -138,13 +138,13 @@
|
||||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||||
|
|
||||||
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
#define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */
|
||||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||||
|
|
||||||
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
#define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */
|
||||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||||
|
|
|
@ -69,15 +69,13 @@
|
||||||
/*
|
/*
|
||||||
* System Peripherals (offset from AT91_BASE_SYS)
|
* System Peripherals (offset from AT91_BASE_SYS)
|
||||||
*/
|
*/
|
||||||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
|
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
|
||||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
|
||||||
|
|
||||||
#define AT91SAM9RL_BASE_DMA 0xffffe600
|
#define AT91SAM9RL_BASE_DMA 0xffffe600
|
||||||
#define AT91SAM9RL_BASE_ECC 0xffffe800
|
#define AT91SAM9RL_BASE_ECC 0xffffe800
|
||||||
|
#define AT91SAM9RL_BASE_SDRAMC 0xffffea00
|
||||||
#define AT91SAM9RL_BASE_SMC 0xffffec00
|
#define AT91SAM9RL_BASE_SMC 0xffffec00
|
||||||
|
#define AT91SAM9RL_BASE_MATRIX 0xffffee00
|
||||||
#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
|
#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
|
||||||
#define AT91SAM9RL_BASE_PIOA 0xfffff400
|
#define AT91SAM9RL_BASE_PIOA 0xfffff400
|
||||||
#define AT91SAM9RL_BASE_PIOB 0xfffff600
|
#define AT91SAM9RL_BASE_PIOB 0xfffff600
|
||||||
|
@ -88,6 +86,7 @@
|
||||||
#define AT91SAM9RL_BASE_RTT 0xfffffd20
|
#define AT91SAM9RL_BASE_RTT 0xfffffd20
|
||||||
#define AT91SAM9RL_BASE_PIT 0xfffffd30
|
#define AT91SAM9RL_BASE_PIT 0xfffffd30
|
||||||
#define AT91SAM9RL_BASE_WDT 0xfffffd40
|
#define AT91SAM9RL_BASE_WDT 0xfffffd40
|
||||||
|
#define AT91SAM9RL_BASE_GPBR 0xfffffd60
|
||||||
#define AT91SAM9RL_BASE_RTC 0xfffffe00
|
#define AT91SAM9RL_BASE_RTC 0xfffffe00
|
||||||
|
|
||||||
#define AT91_USART0 AT91SAM9RL_BASE_US0
|
#define AT91_USART0 AT91SAM9RL_BASE_US0
|
||||||
|
|
|
@ -14,12 +14,12 @@
|
||||||
#ifndef AT91SAM9RL_MATRIX_H
|
#ifndef AT91SAM9RL_MATRIX_H
|
||||||
#define AT91SAM9RL_MATRIX_H
|
#define AT91SAM9RL_MATRIX_H
|
||||||
|
|
||||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||||
|
@ -27,12 +27,12 @@
|
||||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||||
|
|
||||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
|
||||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||||
|
@ -43,12 +43,12 @@
|
||||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||||
|
|
||||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
|
||||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||||
|
@ -56,7 +56,7 @@
|
||||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||||
|
|
||||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||||
|
@ -64,7 +64,7 @@
|
||||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||||
|
|
||||||
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
|
#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
|
||||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||||
|
@ -74,7 +74,7 @@
|
||||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||||
|
|
||||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
|
#define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */
|
||||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||||
|
|
79
arch/arm/mach-at91/include/mach/at91sam9x5.h
Normal file
79
arch/arm/mach-at91/include/mach/at91sam9x5.h
Normal file
|
@ -0,0 +1,79 @@
|
||||||
|
/*
|
||||||
|
* Chip-specific header file for the AT91SAM9x5 family
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||||
|
*
|
||||||
|
* Common definitions.
|
||||||
|
* Based on AT91SAM9x5 datasheet.
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef AT91SAM9X5_H
|
||||||
|
#define AT91SAM9X5_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Peripheral identifiers/interrupts.
|
||||||
|
*/
|
||||||
|
#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
|
||||||
|
#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
|
||||||
|
#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
|
||||||
|
#define AT91SAM9X5_ID_USART0 5 /* USART 0 */
|
||||||
|
#define AT91SAM9X5_ID_USART1 6 /* USART 1 */
|
||||||
|
#define AT91SAM9X5_ID_USART2 7 /* USART 2 */
|
||||||
|
#define AT91SAM9X5_ID_USART3 8 /* USART 3 */
|
||||||
|
#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */
|
||||||
|
#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */
|
||||||
|
#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */
|
||||||
|
#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */
|
||||||
|
#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */
|
||||||
|
#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */
|
||||||
|
#define AT91SAM9X5_ID_UART0 15 /* UART 0 */
|
||||||
|
#define AT91SAM9X5_ID_UART1 16 /* UART 1 */
|
||||||
|
#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||||
|
#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */
|
||||||
|
#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */
|
||||||
|
#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */
|
||||||
|
#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */
|
||||||
|
#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */
|
||||||
|
#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */
|
||||||
|
#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */
|
||||||
|
#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */
|
||||||
|
#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */
|
||||||
|
#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */
|
||||||
|
#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */
|
||||||
|
#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */
|
||||||
|
#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */
|
||||||
|
#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */
|
||||||
|
#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* User Peripheral physical base addresses.
|
||||||
|
*/
|
||||||
|
#define AT91SAM9X5_BASE_USART0 0xf801c000
|
||||||
|
#define AT91SAM9X5_BASE_USART1 0xf8020000
|
||||||
|
#define AT91SAM9X5_BASE_USART2 0xf8024000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* System Peripherals
|
||||||
|
*/
|
||||||
|
#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Base addresses for early serial code (uncompress.h)
|
||||||
|
*/
|
||||||
|
#define AT91_DBGU AT91_BASE_DBGU0
|
||||||
|
#define AT91_USART0 AT91SAM9X5_BASE_USART0
|
||||||
|
#define AT91_USART1 AT91SAM9X5_BASE_USART1
|
||||||
|
#define AT91_USART2 AT91SAM9X5_BASE_USART2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Internal Memory.
|
||||||
|
*/
|
||||||
|
#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||||
|
#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
|
||||||
|
|
||||||
|
#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||||
|
#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
|
||||||
|
|
||||||
|
#endif
|
53
arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
Normal file
53
arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
Normal file
|
@ -0,0 +1,53 @@
|
||||||
|
/*
|
||||||
|
* Matrix-centric header file for the AT91SAM9x5 family
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||||
|
*
|
||||||
|
* Only EBI related registers.
|
||||||
|
* Write Protect register definitions may be useful.
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef AT91SAM9X5_MATRIX_H
|
||||||
|
#define AT91SAM9X5_MATRIX_H
|
||||||
|
|
||||||
|
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
|
||||||
|
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||||
|
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||||
|
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||||
|
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||||
|
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||||
|
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
|
||||||
|
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||||
|
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||||
|
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||||
|
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||||
|
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||||
|
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||||
|
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||||
|
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||||
|
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||||
|
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||||
|
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||||
|
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||||
|
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
|
||||||
|
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
|
||||||
|
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
|
||||||
|
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
|
||||||
|
#define AT91_MATRIX_MP_OFF (0 << 25)
|
||||||
|
#define AT91_MATRIX_MP_ON (1 << 25)
|
||||||
|
|
||||||
|
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||||
|
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||||
|
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||||
|
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||||
|
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||||
|
|
||||||
|
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||||
|
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||||
|
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||||
|
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||||
|
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||||
|
|
||||||
|
#endif
|
|
@ -28,18 +28,18 @@
|
||||||
#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
|
#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* System Peripherals (offset from AT91_BASE_SYS)
|
* System Peripherals
|
||||||
*/
|
*/
|
||||||
#define AT91_BASE_SYS 0xffc00000
|
#define AT91_BASE_SYS 0xffc00000
|
||||||
|
|
||||||
#define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */
|
#define AT91_EBI 0xffe00000 /* External Bus Interface */
|
||||||
#define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */
|
#define AT91_SF 0xfff00000 /* Special Function */
|
||||||
#define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */
|
#define AT91_USART1 0xfffcc000 /* USART 1 */
|
||||||
#define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */
|
#define AT91_USART0 0xfffd0000 /* USART 0 */
|
||||||
#define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */
|
#define AT91_TC 0xfffe0000 /* Timer Counter */
|
||||||
#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */
|
#define AT91_PIOA 0xffff0000 /* PIO Controller A */
|
||||||
#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */
|
#define AT91_PS 0xffff4000 /* Power Save */
|
||||||
#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */
|
#define AT91_WD 0xffff8000 /* Watchdog Timer */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The AT91x40 series doesn't have a debug unit like the other AT91 parts.
|
* The AT91x40 series doesn't have a debug unit like the other AT91 parts.
|
||||||
|
|
|
@ -107,6 +107,8 @@ struct atmel_nand_data {
|
||||||
u8 ale; /* address line number connected to ALE */
|
u8 ale; /* address line number connected to ALE */
|
||||||
u8 cle; /* address line number connected to CLE */
|
u8 cle; /* address line number connected to CLE */
|
||||||
u8 bus_width_16; /* buswidth is 16 bit */
|
u8 bus_width_16; /* buswidth is 16 bit */
|
||||||
|
u8 correction_cap; /* PMECC correction capability */
|
||||||
|
u16 sector_size; /* Sector size for PMECC */
|
||||||
struct mtd_partition *parts;
|
struct mtd_partition *parts;
|
||||||
unsigned int num_parts;
|
unsigned int num_parts;
|
||||||
};
|
};
|
||||||
|
@ -179,7 +181,9 @@ extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
|
||||||
extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
|
extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
|
||||||
|
|
||||||
/* ISI */
|
/* ISI */
|
||||||
extern void __init at91_add_device_isi(void);
|
struct isi_platform_data;
|
||||||
|
extern void __init at91_add_device_isi(struct isi_platform_data *data,
|
||||||
|
bool use_pck_as_mck);
|
||||||
|
|
||||||
/* Touchscreen Controller */
|
/* Touchscreen Controller */
|
||||||
struct at91_tsadcc_data {
|
struct at91_tsadcc_data {
|
||||||
|
|
|
@ -25,7 +25,6 @@
|
||||||
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
|
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
|
||||||
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
|
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
|
||||||
#define ARCH_ID_AT91SAM9X5 0x819a05a0
|
#define ARCH_ID_AT91SAM9X5 0x819a05a0
|
||||||
#define ARCH_ID_AT91CAP9 0x039A03A0
|
|
||||||
|
|
||||||
#define ARCH_ID_AT91SAM9XE128 0x329973a0
|
#define ARCH_ID_AT91SAM9XE128 0x329973a0
|
||||||
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
|
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
|
||||||
|
@ -51,10 +50,6 @@
|
||||||
#define ARCH_FAMILY_AT91SAM9 0x01900000
|
#define ARCH_FAMILY_AT91SAM9 0x01900000
|
||||||
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
|
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
|
||||||
|
|
||||||
/* PMC revision */
|
|
||||||
#define ARCH_REVISION_CAP9_B 0x399
|
|
||||||
#define ARCH_REVISION_CAP9_C 0x601
|
|
||||||
|
|
||||||
/* RM9200 type */
|
/* RM9200 type */
|
||||||
#define ARCH_REVISON_9200_BGA (0 << 0)
|
#define ARCH_REVISON_9200_BGA (0 << 0)
|
||||||
#define ARCH_REVISON_9200_PQFP (1 << 0)
|
#define ARCH_REVISON_9200_PQFP (1 << 0)
|
||||||
|
@ -63,9 +58,6 @@ enum at91_soc_type {
|
||||||
/* 920T */
|
/* 920T */
|
||||||
AT91_SOC_RM9200,
|
AT91_SOC_RM9200,
|
||||||
|
|
||||||
/* CAP */
|
|
||||||
AT91_SOC_CAP9,
|
|
||||||
|
|
||||||
/* SAM92xx */
|
/* SAM92xx */
|
||||||
AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
|
AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
|
||||||
|
|
||||||
|
@ -86,9 +78,6 @@ enum at91_soc_subtype {
|
||||||
/* RM9200 */
|
/* RM9200 */
|
||||||
AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
|
AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
|
||||||
|
|
||||||
/* CAP9 */
|
|
||||||
AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C,
|
|
||||||
|
|
||||||
/* SAM9260 */
|
/* SAM9260 */
|
||||||
AT91_SOC_SAM9XE,
|
AT91_SOC_SAM9XE,
|
||||||
|
|
||||||
|
@ -195,16 +184,6 @@ static inline int at91_soc_is_detected(void)
|
||||||
#define cpu_is_at91sam9x25() (0)
|
#define cpu_is_at91sam9x25() (0)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_AT91CAP9
|
|
||||||
#define cpu_is_at91cap9() (at91_soc_initdata.type == AT91_SOC_CAP9)
|
|
||||||
#define cpu_is_at91cap9_revB() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_B)
|
|
||||||
#define cpu_is_at91cap9_revC() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_C)
|
|
||||||
#else
|
|
||||||
#define cpu_is_at91cap9() (0)
|
|
||||||
#define cpu_is_at91cap9_revB() (0)
|
|
||||||
#define cpu_is_at91cap9_revC() (0)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
||||||
* definitions may reduce clutter in common drivers.
|
* definitions may reduce clutter in common drivers.
|
||||||
|
|
|
@ -19,7 +19,7 @@
|
||||||
/* DBGU base */
|
/* DBGU base */
|
||||||
/* rm9200, 9260/9g20, 9261/9g10, 9rl */
|
/* rm9200, 9260/9g20, 9261/9g10, 9rl */
|
||||||
#define AT91_BASE_DBGU0 0xfffff200
|
#define AT91_BASE_DBGU0 0xfffff200
|
||||||
/* 9263, 9g45, cap9 */
|
/* 9263, 9g45 */
|
||||||
#define AT91_BASE_DBGU1 0xffffee00
|
#define AT91_BASE_DBGU1 0xffffee00
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_AT91RM9200)
|
#if defined(CONFIG_ARCH_AT91RM9200)
|
||||||
|
@ -34,8 +34,8 @@
|
||||||
#include <mach/at91sam9rl.h>
|
#include <mach/at91sam9rl.h>
|
||||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||||
#include <mach/at91sam9g45.h>
|
#include <mach/at91sam9g45.h>
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
#elif defined(CONFIG_ARCH_AT91SAM9X5)
|
||||||
#include <mach/at91cap9.h>
|
#include <mach/at91sam9x5.h>
|
||||||
#elif defined(CONFIG_ARCH_AT91X40)
|
#elif defined(CONFIG_ARCH_AT91X40)
|
||||||
#include <mach/at91x40.h>
|
#include <mach/at91x40.h>
|
||||||
#else
|
#else
|
||||||
|
@ -59,9 +59,10 @@
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* On all at91 have the Advanced Interrupt Controller starts at address
|
* On all at91 have the Advanced Interrupt Controller starts at address
|
||||||
* 0xfffff000
|
* 0xfffff000 and the Power Management Controller starts at 0xfffffc00
|
||||||
*/
|
*/
|
||||||
#define AT91_AIC 0xfffff000
|
#define AT91_AIC 0xfffff000
|
||||||
|
#define AT91_PMC 0xfffffc00
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Peripheral identifiers/interrupts.
|
* Peripheral identifiers/interrupts.
|
||||||
|
|
|
@ -28,22 +28,4 @@
|
||||||
#define __io(a) __typesafe_io(a)
|
#define __io(a) __typesafe_io(a)
|
||||||
#define __mem_pci(a) (a)
|
#define __mem_pci(a) (a)
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
|
|
||||||
static inline unsigned int at91_sys_read(unsigned int reg_offset)
|
|
||||||
{
|
|
||||||
void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
|
|
||||||
|
|
||||||
return __raw_readl(addr + reg_offset);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
|
|
||||||
{
|
|
||||||
void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
|
|
||||||
|
|
||||||
__raw_writel(value, addr + reg_offset);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -1,50 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-at91/include/mach/system.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2003 SAN People
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __ASM_ARCH_SYSTEM_H
|
|
||||||
#define __ASM_ARCH_SYSTEM_H
|
|
||||||
|
|
||||||
#include <mach/hardware.h>
|
|
||||||
#include <mach/at91_st.h>
|
|
||||||
#include <mach/at91_dbgu.h>
|
|
||||||
#include <mach/at91_pmc.h>
|
|
||||||
|
|
||||||
static inline void arch_idle(void)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Disable the processor clock. The processor will be automatically
|
|
||||||
* re-enabled by an interrupt or by a reset.
|
|
||||||
*/
|
|
||||||
#ifdef AT91_PS
|
|
||||||
at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
|
|
||||||
#else
|
|
||||||
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
|
||||||
#endif
|
|
||||||
#ifndef CONFIG_CPU_ARM920T
|
|
||||||
/*
|
|
||||||
* Set the processor (CP15) into 'Wait for Interrupt' mode.
|
|
||||||
* Post-RM9200 processors need this in conjunction with the above
|
|
||||||
* to save power when idle.
|
|
||||||
*/
|
|
||||||
cpu_do_idle();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -136,7 +136,7 @@ static int at91_pm_verify_clocks(void)
|
||||||
unsigned long scsr;
|
unsigned long scsr;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
scsr = at91_sys_read(AT91_PMC_SCSR);
|
scsr = at91_pmc_read(AT91_PMC_SCSR);
|
||||||
|
|
||||||
/* USB must not be using PLLB */
|
/* USB must not be using PLLB */
|
||||||
if (cpu_is_at91rm9200()) {
|
if (cpu_is_at91rm9200()) {
|
||||||
|
@ -150,11 +150,6 @@ static int at91_pm_verify_clocks(void)
|
||||||
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
|
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
} else if (cpu_is_at91cap9()) {
|
|
||||||
if ((scsr & AT91CAP9_PMC_UHP) != 0) {
|
|
||||||
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
|
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
|
||||||
|
@ -165,7 +160,7 @@ static int at91_pm_verify_clocks(void)
|
||||||
if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
|
if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
|
css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
|
||||||
if (css != AT91_PMC_CSS_SLOW) {
|
if (css != AT91_PMC_CSS_SLOW) {
|
||||||
pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
|
pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -193,23 +188,36 @@ int at91_suspend_entering_slow_clock(void)
|
||||||
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
|
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
|
||||||
|
|
||||||
|
|
||||||
static void (*slow_clock)(void);
|
static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
|
||||||
|
void __iomem *ramc1, int memctrl);
|
||||||
|
|
||||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||||
extern void at91_slow_clock(void);
|
extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
|
||||||
|
void __iomem *ramc1, int memctrl);
|
||||||
extern u32 at91_slow_clock_sz;
|
extern u32 at91_slow_clock_sz;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
void __iomem *at91_ramc_base[2];
|
||||||
|
|
||||||
|
void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
|
||||||
|
{
|
||||||
|
if (id < 0 || id > 1) {
|
||||||
|
pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
|
||||||
|
BUG();
|
||||||
|
}
|
||||||
|
at91_ramc_base[id] = ioremap(addr, size);
|
||||||
|
if (!at91_ramc_base[id])
|
||||||
|
panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
|
||||||
|
}
|
||||||
|
|
||||||
static int at91_pm_enter(suspend_state_t state)
|
static int at91_pm_enter(suspend_state_t state)
|
||||||
{
|
{
|
||||||
u32 saved_lpr;
|
|
||||||
at91_gpio_suspend();
|
at91_gpio_suspend();
|
||||||
at91_irq_suspend();
|
at91_irq_suspend();
|
||||||
|
|
||||||
pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
|
pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
|
||||||
/* remember all the always-wake irqs */
|
/* remember all the always-wake irqs */
|
||||||
(at91_sys_read(AT91_PMC_PCSR)
|
(at91_pmc_read(AT91_PMC_PCSR)
|
||||||
| (1 << AT91_ID_FIQ)
|
| (1 << AT91_ID_FIQ)
|
||||||
| (1 << AT91_ID_SYS)
|
| (1 << AT91_ID_SYS)
|
||||||
| (at91_extern_irq))
|
| (at91_extern_irq))
|
||||||
|
@ -234,11 +242,18 @@ static int at91_pm_enter(suspend_state_t state)
|
||||||
* turning off the main oscillator; reverse on wakeup.
|
* turning off the main oscillator; reverse on wakeup.
|
||||||
*/
|
*/
|
||||||
if (slow_clock) {
|
if (slow_clock) {
|
||||||
|
int memctrl = AT91_MEMCTRL_SDRAMC;
|
||||||
|
|
||||||
|
if (cpu_is_at91rm9200())
|
||||||
|
memctrl = AT91_MEMCTRL_MC;
|
||||||
|
else if (cpu_is_at91sam9g45())
|
||||||
|
memctrl = AT91_MEMCTRL_DDRSDR;
|
||||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||||
/* copy slow_clock handler to SRAM, and call it */
|
/* copy slow_clock handler to SRAM, and call it */
|
||||||
memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
|
memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
|
||||||
#endif
|
#endif
|
||||||
slow_clock();
|
slow_clock(at91_pmc_base, at91_ramc_base[0],
|
||||||
|
at91_ramc_base[1], memctrl);
|
||||||
break;
|
break;
|
||||||
} else {
|
} else {
|
||||||
pr_info("AT91: PM - no slow clock mode enabled ...\n");
|
pr_info("AT91: PM - no slow clock mode enabled ...\n");
|
||||||
|
@ -259,16 +274,7 @@ static int at91_pm_enter(suspend_state_t state)
|
||||||
* For ARM 926 based chips, this requirement is weaker
|
* For ARM 926 based chips, this requirement is weaker
|
||||||
* as at91sam9 can access a RAM in self-refresh mode.
|
* as at91sam9 can access a RAM in self-refresh mode.
|
||||||
*/
|
*/
|
||||||
asm volatile ( "mov r0, #0\n\t"
|
at91_standby();
|
||||||
"b 1f\n\t"
|
|
||||||
".align 5\n\t"
|
|
||||||
"1: mcr p15, 0, r0, c7, c10, 4\n\t"
|
|
||||||
: /* no output */
|
|
||||||
: /* no input */
|
|
||||||
: "r0");
|
|
||||||
saved_lpr = sdram_selfrefresh_enable();
|
|
||||||
wait_for_interrupt_enable();
|
|
||||||
sdram_selfrefresh_disable(saved_lpr);
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case PM_SUSPEND_ON:
|
case PM_SUSPEND_ON:
|
||||||
|
@ -316,7 +322,7 @@ static int __init at91_pm_init(void)
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_AT91RM9200
|
#ifdef CONFIG_ARCH_AT91RM9200
|
||||||
/* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
|
/* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
|
||||||
at91_sys_write(AT91_SDRAMC_LPR, 0);
|
at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
suspend_set_ops(&at91_pm_ops);
|
suspend_set_ops(&at91_pm_ops);
|
||||||
|
|
|
@ -1,5 +1,19 @@
|
||||||
|
/*
|
||||||
|
* AT91 Power Management
|
||||||
|
*
|
||||||
|
* Copyright (C) 2005 David Brownell
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*/
|
||||||
|
#ifndef __ARCH_ARM_MACH_AT91_PM
|
||||||
|
#define __ARCH_ARM_MACH_AT91_PM
|
||||||
|
|
||||||
|
#include <mach/at91_ramc.h>
|
||||||
#ifdef CONFIG_ARCH_AT91RM9200
|
#ifdef CONFIG_ARCH_AT91RM9200
|
||||||
#include <mach/at91rm9200_mc.h>
|
#include <mach/at91rm9200_sdramc.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The AT91RM9200 goes into self-refresh mode with this command, and will
|
* The AT91RM9200 goes into self-refresh mode with this command, and will
|
||||||
|
@ -11,51 +25,37 @@
|
||||||
* still in self-refresh is "not recommended", but seems to work.
|
* still in self-refresh is "not recommended", but seems to work.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static inline u32 sdram_selfrefresh_enable(void)
|
static inline void at91rm9200_standby(void)
|
||||||
{
|
{
|
||||||
u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
|
u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
|
||||||
|
|
||||||
at91_sys_write(AT91_SDRAMC_LPR, 0);
|
asm volatile(
|
||||||
at91_sys_write(AT91_SDRAMC_SRR, 1);
|
"b 1f\n\t"
|
||||||
return saved_lpr;
|
".align 5\n\t"
|
||||||
|
"1: mcr p15, 0, %0, c7, c10, 4\n\t"
|
||||||
|
" str %0, [%1, %2]\n\t"
|
||||||
|
" str %3, [%1, %4]\n\t"
|
||||||
|
" mcr p15, 0, %0, c7, c0, 4\n\t"
|
||||||
|
" str %5, [%1, %2]"
|
||||||
|
:
|
||||||
|
: "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
|
||||||
|
"r" (1), "r" (AT91RM9200_SDRAMC_SRR),
|
||||||
|
"r" (lpr));
|
||||||
}
|
}
|
||||||
|
|
||||||
#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
|
#define at91_standby at91rm9200_standby
|
||||||
#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
|
|
||||||
: : "r" (0))
|
|
||||||
|
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
|
||||||
#include <mach/at91sam9_ddrsdr.h>
|
|
||||||
|
|
||||||
|
|
||||||
static inline u32 sdram_selfrefresh_enable(void)
|
|
||||||
{
|
|
||||||
u32 saved_lpr, lpr;
|
|
||||||
|
|
||||||
saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
|
|
||||||
|
|
||||||
lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
|
|
||||||
at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
|
|
||||||
return saved_lpr;
|
|
||||||
}
|
|
||||||
|
|
||||||
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
|
|
||||||
#define wait_for_interrupt_enable() cpu_do_idle()
|
|
||||||
|
|
||||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||||
#include <mach/at91sam9_ddrsdr.h>
|
|
||||||
|
|
||||||
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
|
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
|
||||||
* remember.
|
* remember.
|
||||||
*/
|
*/
|
||||||
static u32 saved_lpr1;
|
static inline void at91sam9g45_standby(void)
|
||||||
|
|
||||||
static inline u32 sdram_selfrefresh_enable(void)
|
|
||||||
{
|
{
|
||||||
/* Those tow values allow us to delay self-refresh activation
|
/* Those two values allow us to delay self-refresh activation
|
||||||
* to the maximum. */
|
* to the maximum. */
|
||||||
u32 lpr0, lpr1;
|
u32 lpr0, lpr1;
|
||||||
u32 saved_lpr0;
|
u32 saved_lpr0, saved_lpr1;
|
||||||
|
|
||||||
saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
|
saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
|
||||||
lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
|
lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
|
||||||
|
@ -69,18 +69,15 @@ static inline u32 sdram_selfrefresh_enable(void)
|
||||||
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
|
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
|
||||||
at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
|
at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
|
||||||
|
|
||||||
return saved_lpr0;
|
cpu_do_idle();
|
||||||
|
|
||||||
|
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
|
||||||
|
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
|
||||||
}
|
}
|
||||||
|
|
||||||
#define sdram_selfrefresh_disable(saved_lpr0) \
|
#define at91_standby at91sam9g45_standby
|
||||||
do { \
|
|
||||||
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
|
|
||||||
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
|
|
||||||
} while (0)
|
|
||||||
#define wait_for_interrupt_enable() cpu_do_idle()
|
|
||||||
|
|
||||||
#else
|
#else
|
||||||
#include <mach/at91sam9_sdramc.h>
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_AT91SAM9263
|
#ifdef CONFIG_ARCH_AT91SAM9263
|
||||||
/*
|
/*
|
||||||
|
@ -90,18 +87,23 @@ static inline u32 sdram_selfrefresh_enable(void)
|
||||||
#warning Assuming EB1 SDRAM controller is *NOT* used
|
#warning Assuming EB1 SDRAM controller is *NOT* used
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static inline u32 sdram_selfrefresh_enable(void)
|
static inline void at91sam9_standby(void)
|
||||||
{
|
{
|
||||||
u32 saved_lpr, lpr;
|
u32 saved_lpr, lpr;
|
||||||
|
|
||||||
saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
|
saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
|
||||||
|
|
||||||
lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
|
lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
|
||||||
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
|
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
|
||||||
return saved_lpr;
|
AT91_SDRAMC_LPCB_SELF_REFRESH);
|
||||||
|
|
||||||
|
cpu_do_idle();
|
||||||
|
|
||||||
|
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
|
||||||
}
|
}
|
||||||
|
|
||||||
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
|
#define at91_standby at91sam9_standby
|
||||||
#define wait_for_interrupt_enable() cpu_do_idle()
|
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -15,15 +15,7 @@
|
||||||
#include <linux/linkage.h>
|
#include <linux/linkage.h>
|
||||||
#include <mach/hardware.h>
|
#include <mach/hardware.h>
|
||||||
#include <mach/at91_pmc.h>
|
#include <mach/at91_pmc.h>
|
||||||
|
#include <mach/at91_ramc.h>
|
||||||
#if defined(CONFIG_ARCH_AT91RM9200)
|
|
||||||
#include <mach/at91rm9200_mc.h>
|
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
|
||||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
|
||||||
#include <mach/at91sam9_ddrsdr.h>
|
|
||||||
#else
|
|
||||||
#include <mach/at91sam9_sdramc.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_AT91SAM9263
|
#ifdef CONFIG_ARCH_AT91SAM9263
|
||||||
|
@ -47,17 +39,23 @@
|
||||||
#define PLLALOCK_TIMEOUT 1000
|
#define PLLALOCK_TIMEOUT 1000
|
||||||
#define PLLBLOCK_TIMEOUT 1000
|
#define PLLBLOCK_TIMEOUT 1000
|
||||||
|
|
||||||
|
pmc .req r0
|
||||||
|
sdramc .req r1
|
||||||
|
ramc1 .req r2
|
||||||
|
memctrl .req r3
|
||||||
|
tmp1 .req r4
|
||||||
|
tmp2 .req r5
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Wait until master clock is ready (after switching master clock source)
|
* Wait until master clock is ready (after switching master clock source)
|
||||||
*/
|
*/
|
||||||
.macro wait_mckrdy
|
.macro wait_mckrdy
|
||||||
mov r4, #MCKRDY_TIMEOUT
|
mov tmp2, #MCKRDY_TIMEOUT
|
||||||
1: sub r4, r4, #1
|
1: sub tmp2, tmp2, #1
|
||||||
cmp r4, #0
|
cmp tmp2, #0
|
||||||
beq 2f
|
beq 2f
|
||||||
ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
|
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||||
tst r3, #AT91_PMC_MCKRDY
|
tst tmp1, #AT91_PMC_MCKRDY
|
||||||
beq 1b
|
beq 1b
|
||||||
2:
|
2:
|
||||||
.endm
|
.endm
|
||||||
|
@ -66,12 +64,12 @@
|
||||||
* Wait until master oscillator has stabilized.
|
* Wait until master oscillator has stabilized.
|
||||||
*/
|
*/
|
||||||
.macro wait_moscrdy
|
.macro wait_moscrdy
|
||||||
mov r4, #MOSCRDY_TIMEOUT
|
mov tmp2, #MOSCRDY_TIMEOUT
|
||||||
1: sub r4, r4, #1
|
1: sub tmp2, tmp2, #1
|
||||||
cmp r4, #0
|
cmp tmp2, #0
|
||||||
beq 2f
|
beq 2f
|
||||||
ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
|
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||||
tst r3, #AT91_PMC_MOSCS
|
tst tmp1, #AT91_PMC_MOSCS
|
||||||
beq 1b
|
beq 1b
|
||||||
2:
|
2:
|
||||||
.endm
|
.endm
|
||||||
|
@ -80,12 +78,12 @@
|
||||||
* Wait until PLLA has locked.
|
* Wait until PLLA has locked.
|
||||||
*/
|
*/
|
||||||
.macro wait_pllalock
|
.macro wait_pllalock
|
||||||
mov r4, #PLLALOCK_TIMEOUT
|
mov tmp2, #PLLALOCK_TIMEOUT
|
||||||
1: sub r4, r4, #1
|
1: sub tmp2, tmp2, #1
|
||||||
cmp r4, #0
|
cmp tmp2, #0
|
||||||
beq 2f
|
beq 2f
|
||||||
ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
|
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||||
tst r3, #AT91_PMC_LOCKA
|
tst tmp1, #AT91_PMC_LOCKA
|
||||||
beq 1b
|
beq 1b
|
||||||
2:
|
2:
|
||||||
.endm
|
.endm
|
||||||
|
@ -94,80 +92,98 @@
|
||||||
* Wait until PLLB has locked.
|
* Wait until PLLB has locked.
|
||||||
*/
|
*/
|
||||||
.macro wait_pllblock
|
.macro wait_pllblock
|
||||||
mov r4, #PLLBLOCK_TIMEOUT
|
mov tmp2, #PLLBLOCK_TIMEOUT
|
||||||
1: sub r4, r4, #1
|
1: sub tmp2, tmp2, #1
|
||||||
cmp r4, #0
|
cmp tmp2, #0
|
||||||
beq 2f
|
beq 2f
|
||||||
ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
|
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||||
tst r3, #AT91_PMC_LOCKB
|
tst tmp1, #AT91_PMC_LOCKB
|
||||||
beq 1b
|
beq 1b
|
||||||
2:
|
2:
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
.text
|
.text
|
||||||
|
|
||||||
|
/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
|
||||||
|
* void __iomem *ramc1, int memctrl)
|
||||||
|
*/
|
||||||
ENTRY(at91_slow_clock)
|
ENTRY(at91_slow_clock)
|
||||||
/* Save registers on stack */
|
/* Save registers on stack */
|
||||||
stmfd sp!, {r0 - r12, lr}
|
stmfd sp!, {r4 - r12, lr}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Register usage:
|
* Register usage:
|
||||||
* R1 = Base address of AT91_PMC
|
* R0 = Base address of AT91_PMC
|
||||||
* R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
|
* R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
|
||||||
* R3 = temporary register
|
* R2 = Base address of second RAM Controller or 0 if not present
|
||||||
|
* R3 = Memory controller
|
||||||
* R4 = temporary register
|
* R4 = temporary register
|
||||||
* R5 = Base address of second RAM Controller or 0 if not present
|
* R5 = temporary register
|
||||||
*/
|
*/
|
||||||
ldr r1, .at91_va_base_pmc
|
|
||||||
ldr r2, .at91_va_base_sdramc
|
|
||||||
ldr r5, .at91_va_base_ramc1
|
|
||||||
|
|
||||||
/* Drain write buffer */
|
/* Drain write buffer */
|
||||||
mov r0, #0
|
mov tmp1, #0
|
||||||
mcr p15, 0, r0, c7, c10, 4
|
mcr p15, 0, tmp1, c7, c10, 4
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_AT91RM9200
|
cmp memctrl, #AT91_MEMCTRL_MC
|
||||||
|
bne ddr_sr_enable
|
||||||
|
|
||||||
|
/*
|
||||||
|
* at91rm9200 Memory controller
|
||||||
|
*/
|
||||||
/* Put SDRAM in self-refresh mode */
|
/* Put SDRAM in self-refresh mode */
|
||||||
mov r3, #1
|
mov tmp1, #1
|
||||||
str r3, [r2, #AT91_SDRAMC_SRR]
|
str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
b sdr_sr_done
|
||||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
|
||||||
|
/*
|
||||||
|
* DDRSDR Memory controller
|
||||||
|
*/
|
||||||
|
ddr_sr_enable:
|
||||||
|
cmp memctrl, #AT91_MEMCTRL_DDRSDR
|
||||||
|
bne sdr_sr_enable
|
||||||
|
|
||||||
/* prepare for DDRAM self-refresh mode */
|
/* prepare for DDRAM self-refresh mode */
|
||||||
ldr r3, [r2, #AT91_DDRSDRC_LPR]
|
ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||||
str r3, .saved_sam9_lpr
|
str tmp1, .saved_sam9_lpr
|
||||||
bic r3, #AT91_DDRSDRC_LPCB
|
bic tmp1, #AT91_DDRSDRC_LPCB
|
||||||
orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||||
|
|
||||||
/* figure out if we use the second ram controller */
|
/* figure out if we use the second ram controller */
|
||||||
cmp r5, #0
|
cmp ramc1, #0
|
||||||
ldrne r4, [r5, #AT91_DDRSDRC_LPR]
|
ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||||
strne r4, .saved_sam9_lpr1
|
strne tmp2, .saved_sam9_lpr1
|
||||||
bicne r4, #AT91_DDRSDRC_LPCB
|
bicne tmp2, #AT91_DDRSDRC_LPCB
|
||||||
orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||||
|
|
||||||
/* Enable DDRAM self-refresh mode */
|
/* Enable DDRAM self-refresh mode */
|
||||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||||
strne r4, [r5, #AT91_DDRSDRC_LPR]
|
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||||
#else
|
|
||||||
|
b sdr_sr_done
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SDRAMC Memory controller
|
||||||
|
*/
|
||||||
|
sdr_sr_enable:
|
||||||
/* Enable SDRAM self-refresh mode */
|
/* Enable SDRAM self-refresh mode */
|
||||||
ldr r3, [r2, #AT91_SDRAMC_LPR]
|
ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
|
||||||
str r3, .saved_sam9_lpr
|
str tmp1, .saved_sam9_lpr
|
||||||
|
|
||||||
bic r3, #AT91_SDRAMC_LPCB
|
bic tmp1, #AT91_SDRAMC_LPCB
|
||||||
orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
|
orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
|
||||||
str r3, [r2, #AT91_SDRAMC_LPR]
|
str tmp1, [sdramc, #AT91_SDRAMC_LPR]
|
||||||
#endif
|
|
||||||
|
|
||||||
|
sdr_sr_done:
|
||||||
/* Save Master clock setting */
|
/* Save Master clock setting */
|
||||||
ldr r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
|
ldr tmp1, [pmc, #AT91_PMC_MCKR]
|
||||||
str r3, .saved_mckr
|
str tmp1, .saved_mckr
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Set the Master clock source to slow clock
|
* Set the Master clock source to slow clock
|
||||||
*/
|
*/
|
||||||
bic r3, r3, #AT91_PMC_CSS
|
bic tmp1, tmp1, #AT91_PMC_CSS
|
||||||
str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
|
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||||
|
|
||||||
wait_mckrdy
|
wait_mckrdy
|
||||||
|
|
||||||
|
@ -177,61 +193,61 @@ ENTRY(at91_slow_clock)
|
||||||
*
|
*
|
||||||
* See AT91RM9200 errata #27 and #28 for details.
|
* See AT91RM9200 errata #27 and #28 for details.
|
||||||
*/
|
*/
|
||||||
mov r3, #0
|
mov tmp1, #0
|
||||||
str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
|
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||||
|
|
||||||
wait_mckrdy
|
wait_mckrdy
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Save PLLA setting and disable it */
|
/* Save PLLA setting and disable it */
|
||||||
ldr r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
|
ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||||
str r3, .saved_pllar
|
str tmp1, .saved_pllar
|
||||||
|
|
||||||
mov r3, #AT91_PMC_PLLCOUNT
|
mov tmp1, #AT91_PMC_PLLCOUNT
|
||||||
orr r3, r3, #(1 << 29) /* bit 29 always set */
|
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
|
||||||
str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
|
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||||
|
|
||||||
/* Save PLLB setting and disable it */
|
/* Save PLLB setting and disable it */
|
||||||
ldr r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
|
ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||||
str r3, .saved_pllbr
|
str tmp1, .saved_pllbr
|
||||||
|
|
||||||
mov r3, #AT91_PMC_PLLCOUNT
|
mov tmp1, #AT91_PMC_PLLCOUNT
|
||||||
str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
|
str tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||||
|
|
||||||
/* Turn off the main oscillator */
|
/* Turn off the main oscillator */
|
||||||
ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
|
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||||
bic r3, r3, #AT91_PMC_MOSCEN
|
bic tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||||
str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
|
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||||
|
|
||||||
/* Wait for interrupt */
|
/* Wait for interrupt */
|
||||||
mcr p15, 0, r0, c7, c0, 4
|
mcr p15, 0, tmp1, c7, c0, 4
|
||||||
|
|
||||||
/* Turn on the main oscillator */
|
/* Turn on the main oscillator */
|
||||||
ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
|
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||||
orr r3, r3, #AT91_PMC_MOSCEN
|
orr tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||||
str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
|
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||||
|
|
||||||
wait_moscrdy
|
wait_moscrdy
|
||||||
|
|
||||||
/* Restore PLLB setting */
|
/* Restore PLLB setting */
|
||||||
ldr r3, .saved_pllbr
|
ldr tmp1, .saved_pllbr
|
||||||
str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
|
str tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||||
|
|
||||||
tst r3, #(AT91_PMC_MUL & 0xff0000)
|
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
|
||||||
bne 1f
|
bne 1f
|
||||||
tst r3, #(AT91_PMC_MUL & ~0xff0000)
|
tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
|
||||||
beq 2f
|
beq 2f
|
||||||
1:
|
1:
|
||||||
wait_pllblock
|
wait_pllblock
|
||||||
2:
|
2:
|
||||||
|
|
||||||
/* Restore PLLA setting */
|
/* Restore PLLA setting */
|
||||||
ldr r3, .saved_pllar
|
ldr tmp1, .saved_pllar
|
||||||
str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
|
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||||
|
|
||||||
tst r3, #(AT91_PMC_MUL & 0xff0000)
|
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
|
||||||
bne 3f
|
bne 3f
|
||||||
tst r3, #(AT91_PMC_MUL & ~0xff0000)
|
tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
|
||||||
beq 4f
|
beq 4f
|
||||||
3:
|
3:
|
||||||
wait_pllalock
|
wait_pllalock
|
||||||
|
@ -244,11 +260,11 @@ ENTRY(at91_slow_clock)
|
||||||
*
|
*
|
||||||
* See AT91RM9200 errata #27 and #28 for details.
|
* See AT91RM9200 errata #27 and #28 for details.
|
||||||
*/
|
*/
|
||||||
ldr r3, .saved_mckr
|
ldr tmp1, .saved_mckr
|
||||||
tst r3, #AT91_PMC_PRES
|
tst tmp1, #AT91_PMC_PRES
|
||||||
beq 2f
|
beq 2f
|
||||||
and r3, r3, #AT91_PMC_PRES
|
and tmp1, tmp1, #AT91_PMC_PRES
|
||||||
str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
|
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||||
|
|
||||||
wait_mckrdy
|
wait_mckrdy
|
||||||
#endif
|
#endif
|
||||||
|
@ -256,32 +272,45 @@ ENTRY(at91_slow_clock)
|
||||||
/*
|
/*
|
||||||
* Restore master clock setting
|
* Restore master clock setting
|
||||||
*/
|
*/
|
||||||
2: ldr r3, .saved_mckr
|
2: ldr tmp1, .saved_mckr
|
||||||
str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
|
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||||
|
|
||||||
wait_mckrdy
|
wait_mckrdy
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_AT91RM9200
|
/*
|
||||||
/* Do nothing - self-refresh is automatically disabled. */
|
* at91rm9200 Memory controller
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
* Do nothing - self-refresh is automatically disabled.
|
||||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
*/
|
||||||
|
cmp memctrl, #AT91_MEMCTRL_MC
|
||||||
|
beq ram_restored
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DDRSDR Memory controller
|
||||||
|
*/
|
||||||
|
cmp memctrl, #AT91_MEMCTRL_DDRSDR
|
||||||
|
bne sdr_en_restore
|
||||||
/* Restore LPR on AT91 with DDRAM */
|
/* Restore LPR on AT91 with DDRAM */
|
||||||
ldr r3, .saved_sam9_lpr
|
ldr tmp1, .saved_sam9_lpr
|
||||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||||
|
|
||||||
/* if we use the second ram controller */
|
/* if we use the second ram controller */
|
||||||
cmp r5, #0
|
cmp ramc1, #0
|
||||||
ldrne r4, .saved_sam9_lpr1
|
ldrne tmp2, .saved_sam9_lpr1
|
||||||
strne r4, [r5, #AT91_DDRSDRC_LPR]
|
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||||
|
|
||||||
#else
|
b ram_restored
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SDRAMC Memory controller
|
||||||
|
*/
|
||||||
|
sdr_en_restore:
|
||||||
/* Restore LPR on AT91 with SDRAM */
|
/* Restore LPR on AT91 with SDRAM */
|
||||||
ldr r3, .saved_sam9_lpr
|
ldr tmp1, .saved_sam9_lpr
|
||||||
str r3, [r2, #AT91_SDRAMC_LPR]
|
str tmp1, [sdramc, #AT91_SDRAMC_LPR]
|
||||||
#endif
|
|
||||||
|
|
||||||
|
ram_restored:
|
||||||
/* Restore registers, and return */
|
/* Restore registers, and return */
|
||||||
ldmfd sp!, {r0 - r12, pc}
|
ldmfd sp!, {r4 - r12, pc}
|
||||||
|
|
||||||
|
|
||||||
.saved_mckr:
|
.saved_mckr:
|
||||||
|
@ -299,27 +328,5 @@ ENTRY(at91_slow_clock)
|
||||||
.saved_sam9_lpr1:
|
.saved_sam9_lpr1:
|
||||||
.word 0
|
.word 0
|
||||||
|
|
||||||
.at91_va_base_pmc:
|
|
||||||
.word AT91_VA_BASE_SYS + AT91_PMC
|
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_AT91RM9200
|
|
||||||
.at91_va_base_sdramc:
|
|
||||||
.word AT91_VA_BASE_SYS
|
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
|
||||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
|
||||||
.at91_va_base_sdramc:
|
|
||||||
.word AT91_VA_BASE_SYS + AT91_DDRSDRC0
|
|
||||||
#else
|
|
||||||
.at91_va_base_sdramc:
|
|
||||||
.word AT91_VA_BASE_SYS + AT91_SDRAMC0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.at91_va_base_ramc1:
|
|
||||||
#if defined(CONFIG_ARCH_AT91SAM9G45)
|
|
||||||
.word AT91_VA_BASE_SYS + AT91_DDRSDRC1
|
|
||||||
#else
|
|
||||||
.word 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
ENTRY(at91_slow_clock_sz)
|
ENTRY(at91_slow_clock_sz)
|
||||||
.word .-at91_slow_clock
|
.word .-at91_slow_clock
|
||||||
|
|
|
@ -86,20 +86,6 @@ static void __init soc_detect(u32 dbgu_base)
|
||||||
socid = cidr & ~AT91_CIDR_VERSION;
|
socid = cidr & ~AT91_CIDR_VERSION;
|
||||||
|
|
||||||
switch (socid) {
|
switch (socid) {
|
||||||
case ARCH_ID_AT91CAP9: {
|
|
||||||
#ifdef CONFIG_AT91_PMC_UNIT
|
|
||||||
u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
|
|
||||||
|
|
||||||
if (pmc_ver == ARCH_REVISION_CAP9_B)
|
|
||||||
at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
|
|
||||||
else if (pmc_ver == ARCH_REVISION_CAP9_C)
|
|
||||||
at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
|
|
||||||
#endif
|
|
||||||
at91_soc_initdata.type = AT91_SOC_CAP9;
|
|
||||||
at91_boot_soc = at91cap9_soc;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
case ARCH_ID_AT91RM9200:
|
case ARCH_ID_AT91RM9200:
|
||||||
at91_soc_initdata.type = AT91_SOC_RM9200;
|
at91_soc_initdata.type = AT91_SOC_RM9200;
|
||||||
at91_boot_soc = at91rm9200_soc;
|
at91_boot_soc = at91rm9200_soc;
|
||||||
|
@ -200,7 +186,6 @@ static void __init soc_detect(u32 dbgu_base)
|
||||||
|
|
||||||
static const char *soc_name[] = {
|
static const char *soc_name[] = {
|
||||||
[AT91_SOC_RM9200] = "at91rm9200",
|
[AT91_SOC_RM9200] = "at91rm9200",
|
||||||
[AT91_SOC_CAP9] = "at91cap9",
|
|
||||||
[AT91_SOC_SAM9260] = "at91sam9260",
|
[AT91_SOC_SAM9260] = "at91sam9260",
|
||||||
[AT91_SOC_SAM9261] = "at91sam9261",
|
[AT91_SOC_SAM9261] = "at91sam9261",
|
||||||
[AT91_SOC_SAM9263] = "at91sam9263",
|
[AT91_SOC_SAM9263] = "at91sam9263",
|
||||||
|
@ -221,8 +206,6 @@ EXPORT_SYMBOL(at91_get_soc_type);
|
||||||
static const char *soc_subtype_name[] = {
|
static const char *soc_subtype_name[] = {
|
||||||
[AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
|
[AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
|
||||||
[AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
|
[AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
|
||||||
[AT91_SOC_CAP9_REV_B] = "at91cap9 revB",
|
|
||||||
[AT91_SOC_CAP9_REV_C] = "at91cap9 revC",
|
|
||||||
[AT91_SOC_SAM9XE] = "at91sam9xe",
|
[AT91_SOC_SAM9XE] = "at91sam9xe",
|
||||||
[AT91_SOC_SAM9G45ES] = "at91sam9g45es",
|
[AT91_SOC_SAM9G45ES] = "at91sam9g45es",
|
||||||
[AT91_SOC_SAM9M10] = "at91sam9m10",
|
[AT91_SOC_SAM9M10] = "at91sam9m10",
|
||||||
|
@ -293,6 +276,15 @@ void __init at91_ioremap_rstc(u32 base_addr)
|
||||||
panic("Impossible to ioremap at91_rstc_base\n");
|
panic("Impossible to ioremap at91_rstc_base\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void __iomem *at91_matrix_base;
|
||||||
|
|
||||||
|
void __init at91_ioremap_matrix(u32 base_addr)
|
||||||
|
{
|
||||||
|
at91_matrix_base = ioremap(base_addr, 512);
|
||||||
|
if (!at91_matrix_base)
|
||||||
|
panic("Impossible to ioremap at91_matrix_base\n");
|
||||||
|
}
|
||||||
|
|
||||||
void __init at91_initialize(unsigned long main_clock)
|
void __init at91_initialize(unsigned long main_clock)
|
||||||
{
|
{
|
||||||
at91_boot_soc.ioremap_registers();
|
at91_boot_soc.ioremap_registers();
|
||||||
|
|
|
@ -13,7 +13,6 @@ struct at91_init_soc {
|
||||||
};
|
};
|
||||||
|
|
||||||
extern struct at91_init_soc at91_boot_soc;
|
extern struct at91_init_soc at91_boot_soc;
|
||||||
extern struct at91_init_soc at91cap9_soc;
|
|
||||||
extern struct at91_init_soc at91rm9200_soc;
|
extern struct at91_init_soc at91rm9200_soc;
|
||||||
extern struct at91_init_soc at91sam9260_soc;
|
extern struct at91_init_soc at91sam9260_soc;
|
||||||
extern struct at91_init_soc at91sam9261_soc;
|
extern struct at91_init_soc at91sam9261_soc;
|
||||||
|
@ -27,10 +26,6 @@ static inline int at91_soc_is_enabled(void)
|
||||||
return at91_boot_soc.init != NULL;
|
return at91_boot_soc.init != NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if !defined(CONFIG_ARCH_AT91CAP9)
|
|
||||||
#define at91cap9_soc at91_boot_soc
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(CONFIG_ARCH_AT91RM9200)
|
#if !defined(CONFIG_ARCH_AT91RM9200)
|
||||||
#define at91rm9200_soc at91_boot_soc
|
#define at91rm9200_soc at91_boot_soc
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -52,27 +52,8 @@
|
||||||
#include <mach/csp/chipcHw_inline.h>
|
#include <mach/csp/chipcHw_inline.h>
|
||||||
#include <mach/csp/tmrHw_reg.h>
|
#include <mach/csp/tmrHw_reg.h>
|
||||||
|
|
||||||
#define AMBA_DEVICE(name, initname, base, plat, size) \
|
static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL);
|
||||||
static struct amba_device name##_device = { \
|
static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL);
|
||||||
.dev = { \
|
|
||||||
.coherent_dma_mask = ~0, \
|
|
||||||
.init_name = initname, \
|
|
||||||
.platform_data = plat \
|
|
||||||
}, \
|
|
||||||
.res = { \
|
|
||||||
.start = MM_ADDR_IO_##base, \
|
|
||||||
.end = MM_ADDR_IO_##base + (size) - 1, \
|
|
||||||
.flags = IORESOURCE_MEM \
|
|
||||||
}, \
|
|
||||||
.dma_mask = ~0, \
|
|
||||||
.irq = { \
|
|
||||||
IRQ_##base \
|
|
||||||
} \
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
|
|
||||||
AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
|
|
||||||
|
|
||||||
static struct clk pll1_clk = {
|
static struct clk pll1_clk = {
|
||||||
.name = "PLL1",
|
.name = "PLL1",
|
||||||
|
|
|
@ -1,28 +0,0 @@
|
||||||
/*
|
|
||||||
*
|
|
||||||
* Copyright (C) 1999 ARM Limited
|
|
||||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
#ifndef __ASM_ARCH_SYSTEM_H
|
|
||||||
#define __ASM_ARCH_SYSTEM_H
|
|
||||||
|
|
||||||
static inline void arch_idle(void)
|
|
||||||
{
|
|
||||||
cpu_do_idle();
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -225,3 +225,19 @@ void clps711x_restart(char mode, const char *cmd)
|
||||||
{
|
{
|
||||||
soft_restart(0);
|
soft_restart(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void clps711x_idle(void)
|
||||||
|
{
|
||||||
|
clps_writel(1, HALT);
|
||||||
|
__asm__ __volatile__(
|
||||||
|
"mov r0, r0\n\
|
||||||
|
mov r0, r0");
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __init clps711x_idle_init(void)
|
||||||
|
{
|
||||||
|
arm_pm_idle = clps711x_idle;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
arch_initcall(clps711x_idle_init);
|
||||||
|
|
|
@ -1,35 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-clps711x/include/mach/system.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
#ifndef __ASM_ARCH_SYSTEM_H
|
|
||||||
#define __ASM_ARCH_SYSTEM_H
|
|
||||||
|
|
||||||
#include <linux/io.h>
|
|
||||||
#include <mach/hardware.h>
|
|
||||||
#include <asm/hardware/clps7111.h>
|
|
||||||
|
|
||||||
static inline void arch_idle(void)
|
|
||||||
{
|
|
||||||
clps_writel(1, HALT);
|
|
||||||
__asm__ __volatile__(
|
|
||||||
"mov r0, r0\n\
|
|
||||||
mov r0, r0");
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -1,25 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2000 Deep Blue Solutions Ltd
|
|
||||||
* Copyright 2003 ARM Limited
|
|
||||||
* Copyright 2008 Cavium Networks
|
|
||||||
*
|
|
||||||
* This file is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License, Version 2, as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __MACH_SYSTEM_H
|
|
||||||
#define __MACH_SYSTEM_H
|
|
||||||
|
|
||||||
#include <asm/proc-fns.h>
|
|
||||||
|
|
||||||
static inline void arch_idle(void)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* This should do all the clock switching
|
|
||||||
* and wait for interrupt tricks
|
|
||||||
*/
|
|
||||||
cpu_do_idle();
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -1,21 +0,0 @@
|
||||||
/*
|
|
||||||
* DaVinci system defines
|
|
||||||
*
|
|
||||||
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
|
|
||||||
*
|
|
||||||
* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
|
||||||
* the terms of the GNU General Public License version 2. This program
|
|
||||||
* is licensed "as is" without any warranty of any kind, whether express
|
|
||||||
* or implied.
|
|
||||||
*/
|
|
||||||
#ifndef __ASM_ARCH_SYSTEM_H
|
|
||||||
#define __ASM_ARCH_SYSTEM_H
|
|
||||||
|
|
||||||
#include <mach/common.h>
|
|
||||||
|
|
||||||
static inline void arch_idle(void)
|
|
||||||
{
|
|
||||||
cpu_do_idle();
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* __ASM_ARCH_SYSTEM_H */
|
|
|
@ -1,17 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-dove/include/mach/system.h
|
|
||||||
*
|
|
||||||
* This file is licensed under the terms of the GNU General Public
|
|
||||||
* License version 2. This program is licensed "as is" without any
|
|
||||||
* warranty of any kind, whether express or implied.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __ASM_ARCH_SYSTEM_H
|
|
||||||
#define __ASM_ARCH_SYSTEM_H
|
|
||||||
|
|
||||||
static inline void arch_idle(void)
|
|
||||||
{
|
|
||||||
cpu_do_idle();
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -271,8 +271,33 @@ static struct platform_device *ebsa110_devices[] = {
|
||||||
&am79c961_device,
|
&am79c961_device,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* EBSA110 idling methodology:
|
||||||
|
*
|
||||||
|
* We can not execute the "wait for interrupt" instruction since that
|
||||||
|
* will stop our MCLK signal (which provides the clock for the glue
|
||||||
|
* logic, and therefore the timer interrupt).
|
||||||
|
*
|
||||||
|
* Instead, we spin, polling the IRQ_STAT register for the occurrence
|
||||||
|
* of any interrupt with core clock down to the memory clock.
|
||||||
|
*/
|
||||||
|
static void ebsa110_idle(void)
|
||||||
|
{
|
||||||
|
const char *irq_stat = (char *)0xff000000;
|
||||||
|
|
||||||
|
/* disable clock switching */
|
||||||
|
asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
|
||||||
|
|
||||||
|
/* wait for an interrupt to occur */
|
||||||
|
while (!*irq_stat);
|
||||||
|
|
||||||
|
/* enable clock switching */
|
||||||
|
asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
|
||||||
|
}
|
||||||
|
|
||||||
static int __init ebsa110_init(void)
|
static int __init ebsa110_init(void)
|
||||||
{
|
{
|
||||||
|
arm_pm_idle = ebsa110_idle;
|
||||||
return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices));
|
return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -1,37 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-ebsa110/include/mach/system.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 1996-2000 Russell King.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License version 2 as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*/
|
|
||||||
#ifndef __ASM_ARCH_SYSTEM_H
|
|
||||||
#define __ASM_ARCH_SYSTEM_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* EBSA110 idling methodology:
|
|
||||||
*
|
|
||||||
* We can not execute the "wait for interrupt" instruction since that
|
|
||||||
* will stop our MCLK signal (which provides the clock for the glue
|
|
||||||
* logic, and therefore the timer interrupt).
|
|
||||||
*
|
|
||||||
* Instead, we spin, polling the IRQ_STAT register for the occurrence
|
|
||||||
* of any interrupt with core clock down to the memory clock.
|
|
||||||
*/
|
|
||||||
static inline void arch_idle(void)
|
|
||||||
{
|
|
||||||
const char *irq_stat = (char *)0xff000000;
|
|
||||||
|
|
||||||
/* disable clock switching */
|
|
||||||
asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
|
|
||||||
|
|
||||||
/* wait for an interrupt to occur */
|
|
||||||
while (!*irq_stat);
|
|
||||||
|
|
||||||
/* enable clock switching */
|
|
||||||
asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -279,48 +279,14 @@ static struct amba_pl010_data ep93xx_uart_data = {
|
||||||
.set_mctrl = ep93xx_uart_set_mctrl,
|
.set_mctrl = ep93xx_uart_set_mctrl,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct amba_device uart1_device = {
|
static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
|
||||||
.dev = {
|
{ IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
|
||||||
.init_name = "apb:uart1",
|
|
||||||
.platform_data = &ep93xx_uart_data,
|
|
||||||
},
|
|
||||||
.res = {
|
|
||||||
.start = EP93XX_UART1_PHYS_BASE,
|
|
||||||
.end = EP93XX_UART1_PHYS_BASE + 0x0fff,
|
|
||||||
.flags = IORESOURCE_MEM,
|
|
||||||
},
|
|
||||||
.irq = { IRQ_EP93XX_UART1, NO_IRQ },
|
|
||||||
.periphid = 0x00041010,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct amba_device uart2_device = {
|
static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
|
||||||
.dev = {
|
{ IRQ_EP93XX_UART2 }, &ep93xx_uart_data);
|
||||||
.init_name = "apb:uart2",
|
|
||||||
.platform_data = &ep93xx_uart_data,
|
|
||||||
},
|
|
||||||
.res = {
|
|
||||||
.start = EP93XX_UART2_PHYS_BASE,
|
|
||||||
.end = EP93XX_UART2_PHYS_BASE + 0x0fff,
|
|
||||||
.flags = IORESOURCE_MEM,
|
|
||||||
},
|
|
||||||
.irq = { IRQ_EP93XX_UART2, NO_IRQ },
|
|
||||||
.periphid = 0x00041010,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct amba_device uart3_device = {
|
|
||||||
.dev = {
|
|
||||||
.init_name = "apb:uart3",
|
|
||||||
.platform_data = &ep93xx_uart_data,
|
|
||||||
},
|
|
||||||
.res = {
|
|
||||||
.start = EP93XX_UART3_PHYS_BASE,
|
|
||||||
.end = EP93XX_UART3_PHYS_BASE + 0x0fff,
|
|
||||||
.flags = IORESOURCE_MEM,
|
|
||||||
},
|
|
||||||
.irq = { IRQ_EP93XX_UART3, NO_IRQ },
|
|
||||||
.periphid = 0x00041010,
|
|
||||||
};
|
|
||||||
|
|
||||||
|
static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
|
||||||
|
{ IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
|
||||||
|
|
||||||
static struct resource ep93xx_rtc_resource[] = {
|
static struct resource ep93xx_rtc_resource[] = {
|
||||||
{
|
{
|
||||||
|
|
|
@ -1,7 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-ep93xx/include/mach/system.h
|
|
||||||
*/
|
|
||||||
static inline void arch_idle(void)
|
|
||||||
{
|
|
||||||
cpu_do_idle();
|
|
||||||
}
|
|
|
@ -201,14 +201,6 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static void exynos_idle(void)
|
|
||||||
{
|
|
||||||
if (!need_resched())
|
|
||||||
cpu_do_idle();
|
|
||||||
|
|
||||||
local_irq_enable();
|
|
||||||
}
|
|
||||||
|
|
||||||
void exynos4_restart(char mode, const char *cmd)
|
void exynos4_restart(char mode, const char *cmd)
|
||||||
{
|
{
|
||||||
__raw_writel(0x1, S5P_SWRESET);
|
__raw_writel(0x1, S5P_SWRESET);
|
||||||
|
@ -467,10 +459,6 @@ early_initcall(exynos4_l2x0_cache_init);
|
||||||
int __init exynos_init(void)
|
int __init exynos_init(void)
|
||||||
{
|
{
|
||||||
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
|
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
|
||||||
|
|
||||||
/* set idle function */
|
|
||||||
pm_idle = exynos_idle;
|
|
||||||
|
|
||||||
return device_register(&exynos4_dev);
|
return device_register(&exynos4_dev);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -74,21 +74,8 @@ struct dma_pl330_platdata exynos4_pdma0_pdata = {
|
||||||
.peri_id = pdma0_peri,
|
.peri_id = pdma0_peri,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct amba_device exynos4_device_pdma0 = {
|
AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0,
|
||||||
.dev = {
|
{IRQ_PDMA0}, &exynos4_pdma0_pdata);
|
||||||
.init_name = "dma-pl330.0",
|
|
||||||
.dma_mask = &dma_dmamask,
|
|
||||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
||||||
.platform_data = &exynos4_pdma0_pdata,
|
|
||||||
},
|
|
||||||
.res = {
|
|
||||||
.start = EXYNOS4_PA_PDMA0,
|
|
||||||
.end = EXYNOS4_PA_PDMA0 + SZ_4K,
|
|
||||||
.flags = IORESOURCE_MEM,
|
|
||||||
},
|
|
||||||
.irq = {IRQ_PDMA0, NO_IRQ},
|
|
||||||
.periphid = 0x00041330,
|
|
||||||
};
|
|
||||||
|
|
||||||
u8 pdma1_peri[] = {
|
u8 pdma1_peri[] = {
|
||||||
DMACH_PCM0_RX,
|
DMACH_PCM0_RX,
|
||||||
|
@ -123,21 +110,8 @@ struct dma_pl330_platdata exynos4_pdma1_pdata = {
|
||||||
.peri_id = pdma1_peri,
|
.peri_id = pdma1_peri,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct amba_device exynos4_device_pdma1 = {
|
AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1,
|
||||||
.dev = {
|
{IRQ_PDMA1}, &exynos4_pdma1_pdata);
|
||||||
.init_name = "dma-pl330.1",
|
|
||||||
.dma_mask = &dma_dmamask,
|
|
||||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
||||||
.platform_data = &exynos4_pdma1_pdata,
|
|
||||||
},
|
|
||||||
.res = {
|
|
||||||
.start = EXYNOS4_PA_PDMA1,
|
|
||||||
.end = EXYNOS4_PA_PDMA1 + SZ_4K,
|
|
||||||
.flags = IORESOURCE_MEM,
|
|
||||||
},
|
|
||||||
.irq = {IRQ_PDMA1, NO_IRQ},
|
|
||||||
.periphid = 0x00041330,
|
|
||||||
};
|
|
||||||
|
|
||||||
static int __init exynos4_dma_init(void)
|
static int __init exynos4_dma_init(void)
|
||||||
{
|
{
|
||||||
|
@ -146,11 +120,11 @@ static int __init exynos4_dma_init(void)
|
||||||
|
|
||||||
dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
|
dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
|
||||||
dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
|
dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
|
||||||
amba_device_register(&exynos4_device_pdma0, &iomem_resource);
|
amba_device_register(&exynos4_pdma0_device, &iomem_resource);
|
||||||
|
|
||||||
dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
|
dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
|
||||||
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
|
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
|
||||||
amba_device_register(&exynos4_device_pdma1, &iomem_resource);
|
amba_device_register(&exynos4_pdma1_device, &iomem_resource);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -1,20 +0,0 @@
|
||||||
/* linux/arch/arm/mach-exynos4/include/mach/system.h
|
|
||||||
*
|
|
||||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
|
||||||
* http://www.samsung.com
|
|
||||||
*
|
|
||||||
* EXYNOS4 - system support header
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License version 2 as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __ASM_ARCH_SYSTEM_H
|
|
||||||
#define __ASM_ARCH_SYSTEM_H __FILE__
|
|
||||||
|
|
||||||
static void arch_idle(void)
|
|
||||||
{
|
|
||||||
/* nothing here yet */
|
|
||||||
}
|
|
||||||
#endif /* __ASM_ARCH_SYSTEM_H */
|
|
|
@ -1,13 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-footbridge/include/mach/system.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 1996-1999 Russell King.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License version 2 as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*/
|
|
||||||
static inline void arch_idle(void)
|
|
||||||
{
|
|
||||||
cpu_do_idle();
|
|
||||||
}
|
|
|
@ -4,7 +4,7 @@
|
||||||
|
|
||||||
# Object file lists.
|
# Object file lists.
|
||||||
|
|
||||||
obj-y := irq.o mm.o time.o devices.o gpio.o
|
obj-y := irq.o mm.o time.o devices.o gpio.o idle.o
|
||||||
|
|
||||||
# Board-specific support
|
# Board-specific support
|
||||||
obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
|
obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
|
||||||
|
|
29
arch/arm/mach-gemini/idle.c
Normal file
29
arch/arm/mach-gemini/idle.c
Normal file
|
@ -0,0 +1,29 @@
|
||||||
|
/*
|
||||||
|
* arch/arm/mach-gemini/idle.c
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <asm/system.h>
|
||||||
|
#include <asm/proc-fns.h>
|
||||||
|
|
||||||
|
static void gemini_idle(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Because of broken hardware we have to enable interrupts or the CPU
|
||||||
|
* will never wakeup... Acctualy it is not very good to enable
|
||||||
|
* interrupts first since scheduler can miss a tick, but there is
|
||||||
|
* no other way around this. Platforms that needs it for power saving
|
||||||
|
* should call enable_hlt() in init code, since by default it is
|
||||||
|
* disabled.
|
||||||
|
*/
|
||||||
|
local_irq_enable();
|
||||||
|
cpu_do_idle();
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __init gemini_idle_init(void)
|
||||||
|
{
|
||||||
|
arm_pm_idle = gemini_idle;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
arch_initcall(gemini_idle_init);
|
|
@ -14,20 +14,6 @@
|
||||||
#include <mach/hardware.h>
|
#include <mach/hardware.h>
|
||||||
#include <mach/global_reg.h>
|
#include <mach/global_reg.h>
|
||||||
|
|
||||||
static inline void arch_idle(void)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Because of broken hardware we have to enable interrupts or the CPU
|
|
||||||
* will never wakeup... Acctualy it is not very good to enable
|
|
||||||
* interrupts here since scheduler can miss a tick, but there is
|
|
||||||
* no other way around this. Platforms that needs it for power saving
|
|
||||||
* should call enable_hlt() in init code, since by default it is
|
|
||||||
* disabled.
|
|
||||||
*/
|
|
||||||
local_irq_enable();
|
|
||||||
cpu_do_idle();
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void arch_reset(char mode, const char *cmd)
|
static inline void arch_reset(char mode, const char *cmd)
|
||||||
{
|
{
|
||||||
__raw_writel(RESET_GLOBAL | RESET_CPU1,
|
__raw_writel(RESET_GLOBAL | RESET_CPU1,
|
||||||
|
|
|
@ -73,8 +73,8 @@ void __init gemini_init_irq(void)
|
||||||
unsigned int i, mode = 0, level = 0;
|
unsigned int i, mode = 0, level = 0;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Disable arch_idle() by default since it is buggy
|
* Disable the idle handler by default since it is buggy
|
||||||
* For more info see arch/arm/mach-gemini/include/mach/system.h
|
* For more info see arch/arm/mach-gemini/idle.c
|
||||||
*/
|
*/
|
||||||
disable_hlt();
|
disable_hlt();
|
||||||
|
|
||||||
|
|
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