[AGPGART] Fix PCI-posting flush typo.
Unfortunately there was a typo in one of the patches I sent, (The one now committed to the agpgart tree). It may cause a bus error on i810 type hardware. Signed-off-by: Thomas Hellstrom <thomas@tungstengraphics.com> Signed-off-by: Dave Jones <davej@redhat.com>
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@ -253,7 +253,7 @@ insert:
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mem->memory[i], mem->type),
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intel_i810_private.registers+I810_PTE_BASE+(j*4));
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}
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readl(intel_i810_private.registers+I810_PTE_BASE+(j-1*4)); /* PCI Posting. */
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readl(intel_i810_private.registers+I810_PTE_BASE+((j-1)*4)); /* PCI Posting. */
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agp_bridge->driver->tlb_flush(mem);
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return 0;
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