clk: uniphier: add clock data for UniPhier SoCs
Add clock data arrays for all UniPhier SoCs with a binding document. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>steinar/wifi_calib_4_9_kernel
Masahiro Yamada
Stephen Boyd
parent
734d82f4a6
commit
7f4d3b52b6
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@ -0,0 +1,134 @@
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UniPhier clock controller
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System clock
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------------
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Required properties:
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- compatible: should be one of the following:
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"socionext,uniphier-sld3-clock" - for sLD3 SoC.
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"socionext,uniphier-ld4-clock" - for LD4 SoC.
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"socionext,uniphier-pro4-clock" - for Pro4 SoC.
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"socionext,uniphier-sld8-clock" - for sLD8 SoC.
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"socionext,uniphier-pro5-clock" - for Pro5 SoC.
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"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-clock" - for LD11 SoC.
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"socionext,uniphier-ld20-clock" - for LD20 SoC.
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- #clock-cells: should be 1.
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Example:
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sysctrl@61840000 {
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compatible = "socionext,uniphier-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x61840000 0x4000>;
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clock {
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compatible = "socionext,uniphier-ld20-clock";
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#clock-cells = <1>;
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};
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other nodes ...
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};
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Provided clocks:
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8: ST DMAC
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12: GIO (Giga bit stream I/O)
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14: USB3 ch0 host
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15: USB3 ch1 host
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16: USB3 ch0 PHY0
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17: USB3 ch0 PHY1
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20: USB3 ch1 PHY0
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21: USB3 ch1 PHY1
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Media I/O (MIO) clock
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---------------------
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Required properties:
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- compatible: should be one of the following:
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"socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
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"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
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"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
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"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
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"socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.
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"socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
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"socionext,uniphier-ld20-mio-clock" - for LD20 SoC.
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- #clock-cells: should be 1.
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Example:
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mioctrl@59810000 {
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compatible = "socionext,uniphier-mioctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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clock {
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compatible = "socionext,uniphier-ld20-mio-clock";
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#clock-cells = <1>;
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};
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other nodes ...
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};
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Provided clocks:
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0: SD ch0 host
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1: eMMC host
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2: SD ch1 host
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7: MIO DMAC
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8: USB2 ch0 host
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9: USB2 ch1 host
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10: USB2 ch2 host
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11: USB2 ch3 host
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12: USB2 ch0 PHY
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13: USB2 ch1 PHY
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14: USB2 ch2 PHY
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15: USB2 ch3 PHY
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Peripheral clock
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----------------
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Required properties:
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- compatible: should be one of the following:
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"socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
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"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
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"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
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"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
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"socionext,uniphier-pro5-peri-clock" - for Pro5 SoC.
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"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
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"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
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- #clock-cells: should be 1.
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Example:
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perictrl@59820000 {
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compatible = "socionext,uniphier-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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clock {
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compatible = "socionext,uniphier-ld20-peri-clock";
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#clock-cells = <1>;
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};
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other nodes ...
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};
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Provided clocks:
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0: UART ch0
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1: UART ch1
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2: UART ch2
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3: UART ch3
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4: I2C ch0
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5: I2C ch1
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6: I2C ch2
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7: I2C ch3
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8: I2C ch4
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9: I2C ch5
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10: I2C ch6
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@ -3,3 +3,6 @@ obj-y += clk-uniphier-fixed-factor.o
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obj-y += clk-uniphier-fixed-rate.o
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obj-y += clk-uniphier-gate.o
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obj-y += clk-uniphier-mux.o
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obj-y += clk-uniphier-sys.o
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obj-y += clk-uniphier-mio.o
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obj-y += clk-uniphier-peri.o
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@ -109,6 +109,97 @@ static int uniphier_clk_remove(struct platform_device *pdev)
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}
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static const struct of_device_id uniphier_clk_match[] = {
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/* System clock */
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{
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.compatible = "socionext,uniphier-ld4-clock",
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.data = uniphier_ld4_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-clock",
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.data = uniphier_pro4_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-clock",
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.data = uniphier_sld8_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-clock",
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.data = uniphier_pro5_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-clock",
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.data = uniphier_pxs2_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-clock",
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.data = uniphier_ld11_sys_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-clock",
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.data = uniphier_ld20_sys_clk_data,
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},
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/* Media I/O clock */
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{
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.compatible = "socionext,uniphier-sld3-mio-clock",
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.data = uniphier_sld3_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld4-mio-clock",
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.data = uniphier_sld3_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-mio-clock",
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.data = uniphier_sld3_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-mio-clock",
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.data = uniphier_sld3_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-mio-clock",
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.data = uniphier_pro5_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-mio-clock",
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.data = uniphier_pro5_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-mio-clock",
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.data = uniphier_sld3_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-mio-clock",
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.data = uniphier_pro5_mio_clk_data,
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},
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/* Peripheral clock */
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{
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.compatible = "socionext,uniphier-ld4-peri-clock",
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.data = uniphier_ld4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-peri-clock",
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.data = uniphier_ld4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-peri-clock",
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.data = uniphier_pro4_peri_clk_data,
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},
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{ /* sentinel */ }
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};
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@ -0,0 +1,101 @@
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "clk-uniphier.h"
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#define UNIPHIER_MIO_CLK_SD_FIXED \
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UNIPHIER_CLK_FACTOR("sd-44m", -1, "sd-133m", 1, 3), \
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UNIPHIER_CLK_FACTOR("sd-33m", -1, "sd-200m", 1, 6), \
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UNIPHIER_CLK_FACTOR("sd-50m", -1, "sd-200m", 1, 4), \
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UNIPHIER_CLK_FACTOR("sd-67m", -1, "sd-200m", 1, 3), \
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UNIPHIER_CLK_FACTOR("sd-100m", -1, "sd-200m", 1, 2), \
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UNIPHIER_CLK_FACTOR("sd-40m", -1, "sd-200m", 1, 5), \
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UNIPHIER_CLK_FACTOR("sd-25m", -1, "sd-200m", 1, 8), \
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UNIPHIER_CLK_FACTOR("sd-22m", -1, "sd-133m", 1, 6)
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#define UNIPHIER_MIO_CLK_SD(_idx, ch) \
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{ \
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.name = "sd" #ch "-sel", \
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.type = UNIPHIER_CLK_TYPE_MUX, \
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.idx = -1, \
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.data.mux = { \
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.parent_names = { \
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"sd-44m", \
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"sd-33m", \
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"sd-50m", \
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"sd-67m", \
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"sd-100m", \
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"sd-40m", \
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"sd-25m", \
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"sd-22m", \
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}, \
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.num_parents = 8, \
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.reg = 0x30 + 0x200 * (ch), \
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.masks = { \
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0x00031000, \
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0x00031000, \
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0x00031000, \
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0x00031000, \
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0x00001300, \
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0x00001300, \
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0x00001300, \
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0x00001300, \
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}, \
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.vals = { \
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0x00000000, \
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0x00010000, \
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0x00020000, \
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0x00030000, \
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0x00001000, \
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0x00001100, \
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0x00001200, \
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0x00001300, \
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}, \
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}, \
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}, \
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UNIPHIER_CLK_GATE("sd" #ch, (_idx), "sd" #ch "-sel", 0x20 + 0x200 * (ch), 8)
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#define UNIPHIER_MIO_CLK_USB2(idx, ch) \
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UNIPHIER_CLK_GATE("usb2" #ch, (idx), "usb2", 0x20 + 0x200 * (ch), 28)
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#define UNIPHIER_MIO_CLK_USB2_PHY(idx, ch) \
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UNIPHIER_CLK_GATE("usb2" #ch "-phy", (idx), "usb2", 0x20 + 0x200 * (ch), 29)
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#define UNIPHIER_MIO_CLK_DMAC(idx) \
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UNIPHIER_CLK_GATE("miodmac", (idx), "stdmac", 0x20, 25)
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const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = {
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UNIPHIER_MIO_CLK_SD_FIXED,
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UNIPHIER_MIO_CLK_SD(0, 0),
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UNIPHIER_MIO_CLK_SD(1, 1),
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UNIPHIER_MIO_CLK_SD(2, 2),
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UNIPHIER_MIO_CLK_DMAC(7),
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UNIPHIER_MIO_CLK_USB2(8, 0),
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UNIPHIER_MIO_CLK_USB2(9, 1),
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UNIPHIER_MIO_CLK_USB2(10, 2),
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UNIPHIER_MIO_CLK_USB2(11, 3),
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UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
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UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
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UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
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UNIPHIER_MIO_CLK_USB2_PHY(15, 3),
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{ /* sentinel */ }
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};
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const struct uniphier_clk_data uniphier_pro5_mio_clk_data[] = {
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UNIPHIER_MIO_CLK_SD_FIXED,
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UNIPHIER_MIO_CLK_SD(0, 0),
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UNIPHIER_MIO_CLK_SD(1, 1),
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{ /* sentinel */ }
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};
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@ -0,0 +1,57 @@
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "clk-uniphier.h"
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#define UNIPHIER_PERI_CLK_UART(idx, ch) \
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UNIPHIER_CLK_GATE("uart" #ch, (idx), "uart", 0x24, 19 + (ch))
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#define UNIPHIER_PERI_CLK_I2C_COMMON \
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UNIPHIER_CLK_GATE("i2c-common", -1, "i2c", 0x20, 1)
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#define UNIPHIER_PERI_CLK_I2C(idx, ch) \
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UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c-common", 0x24, 5 + (ch))
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#define UNIPHIER_PERI_CLK_FI2C(idx, ch) \
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UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
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const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
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UNIPHIER_PERI_CLK_UART(0, 0),
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UNIPHIER_PERI_CLK_UART(1, 1),
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UNIPHIER_PERI_CLK_UART(2, 2),
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UNIPHIER_PERI_CLK_UART(3, 3),
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UNIPHIER_PERI_CLK_I2C_COMMON,
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UNIPHIER_PERI_CLK_I2C(4, 0),
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UNIPHIER_PERI_CLK_I2C(5, 1),
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UNIPHIER_PERI_CLK_I2C(6, 2),
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UNIPHIER_PERI_CLK_I2C(7, 3),
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UNIPHIER_PERI_CLK_I2C(8, 4),
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{ /* sentinel */ }
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};
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const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
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UNIPHIER_PERI_CLK_UART(0, 0),
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UNIPHIER_PERI_CLK_UART(1, 1),
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UNIPHIER_PERI_CLK_UART(2, 2),
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UNIPHIER_PERI_CLK_UART(3, 3),
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UNIPHIER_PERI_CLK_FI2C(4, 0),
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UNIPHIER_PERI_CLK_FI2C(5, 1),
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UNIPHIER_PERI_CLK_FI2C(6, 2),
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UNIPHIER_PERI_CLK_FI2C(7, 3),
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UNIPHIER_PERI_CLK_FI2C(8, 4),
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UNIPHIER_PERI_CLK_FI2C(9, 5),
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UNIPHIER_PERI_CLK_FI2C(10, 6),
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{ /* sentinel */ }
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};
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@ -0,0 +1,151 @@
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||
*/
|
||||
|
||||
#include <linux/stddef.h>
|
||||
|
||||
#include "clk-uniphier.h"
|
||||
|
||||
#define UNIPHIER_SLD3_SYS_CLK_SD \
|
||||
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
|
||||
UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
|
||||
|
||||
#define UNIPHIER_PRO5_SYS_CLK_SD \
|
||||
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
|
||||
UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
|
||||
|
||||
#define UNIPHIER_LD20_SYS_CLK_SD \
|
||||
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
|
||||
UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
|
||||
|
||||
#define UNIPHIER_SLD3_SYS_CLK_STDMAC(idx) \
|
||||
UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
|
||||
|
||||
#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
|
||||
UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
|
||||
|
||||
#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
|
||||
UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
|
||||
|
||||
#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
|
||||
UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
|
||||
|
||||
const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = {
|
||||
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
|
||||
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
|
||||
UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
|
||||
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
|
||||
UNIPHIER_SLD3_SYS_CLK_SD,
|
||||
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
|
||||
UNIPHIER_SLD3_SYS_CLK_STDMAC(8),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
|
||||
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
|
||||
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
|
||||
UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
|
||||
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
|
||||
UNIPHIER_SLD3_SYS_CLK_SD,
|
||||
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
|
||||
UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
|
||||
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
|
||||
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
|
||||
UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
|
||||
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
|
||||
UNIPHIER_SLD3_SYS_CLK_SD,
|
||||
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
|
||||
UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
|
||||
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
|
||||
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
|
||||
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
|
||||
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
|
||||
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
|
||||
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
|
||||
UNIPHIER_SLD3_SYS_CLK_SD,
|
||||
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
|
||||
UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
|
||||
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
|
||||
UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
|
||||
UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
|
||||
UNIPHIER_PRO5_SYS_CLK_SD,
|
||||
UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC */
|
||||
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
|
||||
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
|
||||
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
|
||||
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
|
||||
UNIPHIER_PRO5_SYS_CLK_SD,
|
||||
UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, RLE */
|
||||
/* GIO is always clock-enabled: no function for 0x2104 bit6 */
|
||||
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
|
||||
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
|
||||
/* The document mentions 0x2104 bit 18, but not functional */
|
||||
UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
|
||||
UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
|
||||
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
|
||||
UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
|
||||
UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
|
||||
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
|
||||
UNIPHIER_LD20_SYS_CLK_SD,
|
||||
UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
|
||||
/* GIO is always clock-enabled: no function for 0x210c bit5 */
|
||||
/*
|
||||
* clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
|
||||
* We do not use bit 15 here.
|
||||
*/
|
||||
UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
|
||||
UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
|
||||
UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
@ -106,4 +106,17 @@ struct clk_hw *uniphier_clk_register_mux(struct device *dev,
|
|||
const char *name,
|
||||
const struct uniphier_clk_mux_data *data);
|
||||
|
||||
extern const struct uniphier_clk_data uniphier_sld3_sys_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_pro5_mio_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
|
||||
extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
|
||||
|
||||
#endif /* __CLK_UNIPHIER_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue