NVMe: Correct the Controller Configuration settings
The arbitration field was extended by one bit, shifting the shutdown notification bits by one. Also, the SQ/CQ entry size was made configurable for future extensions. Reported-by: Paul Luse <paul.e.luse@intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
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@ -905,6 +905,7 @@ static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
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dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
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dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
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dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
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dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
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writel(0, &dev->bar->cc);
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writel(aqa, &dev->bar->aqa);
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@ -41,10 +41,12 @@ enum {
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NVME_CC_MPS_SHIFT = 7,
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NVME_CC_ARB_RR = 0 << 11,
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NVME_CC_ARB_WRRU = 1 << 11,
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NVME_CC_ARB_VS = 3 << 11,
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NVME_CC_SHN_NONE = 0 << 13,
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NVME_CC_SHN_NORMAL = 1 << 13,
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NVME_CC_SHN_ABRUPT = 2 << 13,
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NVME_CC_ARB_VS = 7 << 11,
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NVME_CC_SHN_NONE = 0 << 14,
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NVME_CC_SHN_NORMAL = 1 << 14,
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NVME_CC_SHN_ABRUPT = 2 << 14,
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NVME_CC_IOSQES = 6 << 16,
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NVME_CC_IOCQES = 4 << 20,
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NVME_CSTS_RDY = 1 << 0,
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NVME_CSTS_CFS = 1 << 1,
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NVME_CSTS_SHST_NORMAL = 0 << 2,
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