[TG3]: TSO workaround fixes.
1. Add race condition check after netif_stop_queue(). tg3_tx() runs without netif_tx_lock and can race with tg3_start_xmit_dma_bug() -> tg3_tso_bug(). 2. Firmware TSO in 5703/5704/5705 also have the same TSO limitation, i.e. they cannot handle TSO headers bigger than 80 bytes. Rename TG3_FL2_HW_TSO_1_BUG to TG3_FL2_TSO_BUG and set this flag on these chips as well. 3. Update version to 3.74. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -64,8 +64,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.73"
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#define DRV_MODULE_RELDATE "February 12, 2007"
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#define DRV_MODULE_VERSION "3.74"
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#define DRV_MODULE_RELDATE "February 20, 2007"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@ -3993,7 +3993,10 @@ static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
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/* Estimate the number of fragments in the worst case */
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if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
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netif_stop_queue(tp->dev);
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return NETDEV_TX_BUSY;
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if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
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return NETDEV_TX_BUSY;
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netif_wake_queue(tp->dev);
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}
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segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
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@ -4061,7 +4064,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
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hdr_len = ip_tcp_len + tcp_opt_len;
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if (unlikely((ETH_HLEN + hdr_len) > 80) &&
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(tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
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(tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
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return (tg3_tso_bug(tp, skb));
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base_flags |= (TXD_FLAG_CPU_PRE_DMA |
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@ -8137,7 +8140,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
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(ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
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(ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
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(ering->tx_pending <= MAX_SKB_FRAGS) ||
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((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
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((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
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(ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
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return -EINVAL;
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@ -10557,12 +10560,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
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tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
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} else {
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
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TG3_FLG2_HW_TSO_1_BUG;
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
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ASIC_REV_5750 &&
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tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
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tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
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tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
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}
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}
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@ -11867,7 +11869,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
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tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
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} else {
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tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
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tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
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}
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/* TSO is on by default on chips that support hardware TSO.
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@ -2227,7 +2227,7 @@ struct tg3 {
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#define TG3_FLAG_INIT_COMPLETE 0x80000000
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u32 tg3_flags2;
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#define TG3_FLG2_RESTART_TIMER 0x00000001
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#define TG3_FLG2_HW_TSO_1_BUG 0x00000002
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#define TG3_FLG2_TSO_BUG 0x00000002
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#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
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#define TG3_FLG2_IS_5788 0x00000008
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#define TG3_FLG2_MAX_RXPEND_64 0x00000010
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