clocksource/drivers/rda: Add clock driver for RDA8810PL SoC
Add clock driver for RDA Micro RDA8810PL SoC supporting OSTIMER and HWTIMER. RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER (64 bit). Each timer provides optional interrupt support. In this driver, OSTIMER is used for clockevents and HWTIMER is used for clocksource. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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@ -105,6 +105,14 @@ config OWL_TIMER
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help
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Enables the support for the Actions Semi Owl timer driver.
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config RDA_TIMER
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bool "RDA timer driver" if COMPILE_TEST
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depends on GENERIC_CLOCKEVENTS
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select CLKSRC_MMIO
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select TIMER_OF
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help
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Enables the support for the RDA Micro timer driver.
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config SUN4I_TIMER
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bool "Sun4i timer driver" if COMPILE_TEST
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depends on HAS_IOMEM
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@ -57,6 +57,7 @@ obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
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obj-$(CONFIG_OWL_TIMER) += timer-owl.o
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obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
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obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
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obj-$(CONFIG_RDA_TIMER) += timer-rda.o
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obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
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obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
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195
drivers/clocksource/timer-rda.c
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195
drivers/clocksource/timer-rda.c
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@ -0,0 +1,195 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* RDA8810PL SoC timer driver
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*
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* Copyright RDA Microelectronics Company Limited
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* Copyright (c) 2017 Andreas Färber
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* Copyright (c) 2018 Manivannan Sadhasivam
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*
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* RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER (64 bit).
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* Each timer provides optional interrupt support. In this driver, OSTIMER is
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* used for clockevents and HWTIMER is used for clocksource.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include "timer-of.h"
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#define RDA_OSTIMER_LOADVAL_L 0x000
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#define RDA_OSTIMER_CTRL 0x004
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#define RDA_HWTIMER_LOCKVAL_L 0x024
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#define RDA_HWTIMER_LOCKVAL_H 0x028
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#define RDA_TIMER_IRQ_MASK_SET 0x02c
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#define RDA_TIMER_IRQ_MASK_CLR 0x030
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#define RDA_TIMER_IRQ_CLR 0x034
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#define RDA_OSTIMER_CTRL_ENABLE BIT(24)
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#define RDA_OSTIMER_CTRL_REPEAT BIT(28)
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#define RDA_OSTIMER_CTRL_LOAD BIT(30)
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#define RDA_TIMER_IRQ_MASK_OSTIMER BIT(0)
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#define RDA_TIMER_IRQ_CLR_OSTIMER BIT(0)
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static int rda_ostimer_start(void __iomem *base, bool periodic, u64 cycles)
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{
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u32 ctrl, load_l;
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load_l = (u32)cycles;
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ctrl = ((cycles >> 32) & 0xffffff);
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ctrl |= RDA_OSTIMER_CTRL_LOAD | RDA_OSTIMER_CTRL_ENABLE;
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if (periodic)
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ctrl |= RDA_OSTIMER_CTRL_REPEAT;
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/* Enable ostimer interrupt first */
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writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER,
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base + RDA_TIMER_IRQ_MASK_SET);
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/* Write low 32 bits first, high 24 bits are with ctrl */
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writel_relaxed(load_l, base + RDA_OSTIMER_LOADVAL_L);
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writel_relaxed(ctrl, base + RDA_OSTIMER_CTRL);
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return 0;
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}
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static int rda_ostimer_stop(void __iomem *base)
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{
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/* Disable ostimer interrupt first */
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writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER,
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base + RDA_TIMER_IRQ_MASK_CLR);
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writel_relaxed(0, base + RDA_OSTIMER_CTRL);
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return 0;
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}
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static int rda_ostimer_set_state_shutdown(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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rda_ostimer_stop(timer_of_base(to));
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return 0;
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}
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static int rda_ostimer_set_state_oneshot(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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rda_ostimer_stop(timer_of_base(to));
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return 0;
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}
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static int rda_ostimer_set_state_periodic(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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unsigned long cycles_per_jiffy;
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rda_ostimer_stop(timer_of_base(to));
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cycles_per_jiffy = ((unsigned long long)NSEC_PER_SEC / HZ *
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evt->mult) >> evt->shift;
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rda_ostimer_start(timer_of_base(to), true, cycles_per_jiffy);
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return 0;
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}
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static int rda_ostimer_tick_resume(struct clock_event_device *evt)
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{
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return 0;
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}
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static int rda_ostimer_set_next_event(unsigned long evt,
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struct clock_event_device *ev)
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{
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struct timer_of *to = to_timer_of(ev);
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rda_ostimer_start(timer_of_base(to), false, evt);
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return 0;
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}
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static irqreturn_t rda_ostimer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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struct timer_of *to = to_timer_of(evt);
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/* clear timer int */
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writel_relaxed(RDA_TIMER_IRQ_CLR_OSTIMER,
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timer_of_base(to) + RDA_TIMER_IRQ_CLR);
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if (evt->event_handler)
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct timer_of rda_ostimer_of = {
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE,
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.clkevt = {
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.name = "rda-ostimer",
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.rating = 250,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ,
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.set_state_shutdown = rda_ostimer_set_state_shutdown,
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.set_state_oneshot = rda_ostimer_set_state_oneshot,
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.set_state_periodic = rda_ostimer_set_state_periodic,
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.tick_resume = rda_ostimer_tick_resume,
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.set_next_event = rda_ostimer_set_next_event,
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},
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.of_base = {
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.name = "rda-timer",
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.index = 0,
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},
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.of_irq = {
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.name = "ostimer",
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.handler = rda_ostimer_interrupt,
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.flags = IRQF_TIMER,
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},
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};
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static u64 rda_hwtimer_read(struct clocksource *cs)
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{
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void __iomem *base = timer_of_base(&rda_ostimer_of);
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u32 lo, hi;
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/* Always read low 32 bits first */
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do {
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lo = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_L);
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hi = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H);
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} while (hi != readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H));
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return ((u64)hi << 32) | lo;
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}
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static struct clocksource rda_hwtimer_clocksource = {
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.name = "rda-timer",
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.rating = 400,
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.read = rda_hwtimer_read,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init rda_timer_init(struct device_node *np)
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{
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unsigned long rate = 2000000;
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int ret;
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ret = timer_of_init(np, &rda_ostimer_of);
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if (ret)
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return ret;
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clocksource_register_hz(&rda_hwtimer_clocksource, rate);
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clockevents_config_and_register(&rda_ostimer_of.clkevt, rate,
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0x2, UINT_MAX);
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return 0;
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}
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TIMER_OF_DECLARE(rda8810pl, "rda,8810pl-timer", rda_timer_init);
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