MIPS: Alchemy: Rewrite UART setup and constants.
Detect CPU type at runtime and setup uarts accordingly; also clean up the uart base address mess in the process as far as possible. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2352/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
adcb86279f
commit
80130204b4
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@ -30,21 +30,12 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
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#ifdef CONFIG_SERIAL_8250
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switch (state) {
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case 0:
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if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) {
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/* power-on sequence as suggested in the databooks */
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__raw_writel(0, port->membase + UART_MOD_CNTRL);
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wmb();
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__raw_writel(1, port->membase + UART_MOD_CNTRL);
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wmb();
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}
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__raw_writel(3, port->membase + UART_MOD_CNTRL); /* full on */
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wmb();
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alchemy_uart_enable(CPHYSADDR(port->membase));
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serial8250_do_pm(port, state, old_state);
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break;
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case 3: /* power off */
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serial8250_do_pm(port, state, old_state);
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__raw_writel(0, port->membase + UART_MOD_CNTRL);
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wmb();
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alchemy_uart_disable(CPHYSADDR(port->membase));
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break;
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default:
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serial8250_do_pm(port, state, old_state);
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@ -65,38 +56,60 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
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.pm = alchemy_8250_pm, \
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}
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static struct plat_serial8250_port au1x00_uart_data[] = {
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#if defined(CONFIG_SOC_AU1000)
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PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
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PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
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PORT(UART2_PHYS_ADDR, AU1000_UART2_INT),
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PORT(UART3_PHYS_ADDR, AU1000_UART3_INT),
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#elif defined(CONFIG_SOC_AU1500)
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PORT(UART0_PHYS_ADDR, AU1500_UART0_INT),
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PORT(UART3_PHYS_ADDR, AU1500_UART3_INT),
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#elif defined(CONFIG_SOC_AU1100)
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PORT(UART0_PHYS_ADDR, AU1100_UART0_INT),
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PORT(UART1_PHYS_ADDR, AU1100_UART1_INT),
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PORT(UART3_PHYS_ADDR, AU1100_UART3_INT),
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#elif defined(CONFIG_SOC_AU1550)
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PORT(UART0_PHYS_ADDR, AU1550_UART0_INT),
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PORT(UART1_PHYS_ADDR, AU1550_UART1_INT),
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PORT(UART3_PHYS_ADDR, AU1550_UART3_INT),
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#elif defined(CONFIG_SOC_AU1200)
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PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
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PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
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#endif
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{ },
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static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
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[ALCHEMY_CPU_AU1000] = {
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PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT),
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PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT),
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PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT),
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PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT),
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},
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[ALCHEMY_CPU_AU1500] = {
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PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT),
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PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT),
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},
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[ALCHEMY_CPU_AU1100] = {
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PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT),
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PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT),
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PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT),
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},
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[ALCHEMY_CPU_AU1550] = {
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PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT),
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PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT),
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PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT),
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},
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[ALCHEMY_CPU_AU1200] = {
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PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
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PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
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},
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};
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static struct platform_device au1xx0_uart_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_AU1X00,
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.dev = {
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.platform_data = au1x00_uart_data,
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},
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};
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static void __init alchemy_setup_uarts(int ctype)
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{
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unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
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int s = sizeof(struct plat_serial8250_port);
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int c = alchemy_get_uarts(ctype);
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struct plat_serial8250_port *ports;
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ports = kzalloc(s * (c + 1), GFP_KERNEL);
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if (!ports) {
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printk(KERN_INFO "Alchemy: no memory for UART data\n");
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return;
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}
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memcpy(ports, au1x00_uart_data[ctype], s * c);
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au1xx0_uart_device.dev.platform_data = ports;
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/* Fill up uartclk. */
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for (s = 0; s < c; s++)
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ports[s].uartclk = uartclk;
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if (platform_device_register(&au1xx0_uart_device))
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printk(KERN_INFO "Alchemy: failed to register UARTs\n");
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}
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/* OHCI (USB full speed host controller) */
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static struct resource au1xxx_usb_ohci_resources[] = {
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[0] = {
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@ -442,7 +455,6 @@ void __init au1xxx_override_eth_cfg(unsigned int port,
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}
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static struct platform_device *au1xxx_platform_devices[] __initdata = {
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&au1xx0_uart_device,
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&au1xxx_usb_ohci_device,
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#ifdef CONFIG_FB_AU1100
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&au1100_lcd_device,
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@ -465,13 +477,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
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static int __init au1xxx_platform_init(void)
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{
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unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
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int err, i;
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int err, i, ctype = alchemy_get_cputype();
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unsigned char ethaddr[6];
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/* Fill up uartclk. */
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for (i = 0; au1x00_uart_data[i].flags; i++)
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au1x00_uart_data[i].uartclk = uartclk;
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alchemy_setup_uarts(ctype);
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/* use firmware-provided mac addr if available and necessary */
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i = prom_get_ethernet_addr(ethaddr);
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@ -62,5 +62,5 @@ void __init prom_init(void)
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void prom_putchar(unsigned char c)
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{
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alchemy_uart_putchar(UART0_PHYS_ADDR, c);
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alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
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}
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@ -36,9 +36,6 @@
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#include <prom.h>
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#define UART1_ADDR KSEG1ADDR(UART1_PHYS_ADDR)
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#define UART3_ADDR KSEG1ADDR(UART3_PHYS_ADDR)
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char irq_tab_alchemy[][5] __initdata = {
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[0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
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};
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@ -67,18 +64,15 @@ static void gpr_power_off(void)
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void __init board_setup(void)
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{
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printk(KERN_INFO "Tarpeze ITS GPR board\n");
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printk(KERN_INFO "Trapeze ITS GPR board\n");
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pm_power_off = gpr_power_off;
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_machine_halt = gpr_power_off;
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_machine_restart = gpr_reset;
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/* Enable UART3 */
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au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */
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au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
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/* Enable UART1 */
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au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
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au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
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/* Enable UART1/3 */
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alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
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alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
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/* Take away Reset of UMTS-card */
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alchemy_gpio_direction_output(215, 1);
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@ -59,5 +59,5 @@ void __init prom_init(void)
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void prom_putchar(unsigned char c)
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{
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alchemy_uart_putchar(UART0_PHYS_ADDR, c);
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alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
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}
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@ -62,5 +62,5 @@ void __init prom_init(void)
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void prom_putchar(unsigned char c)
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{
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alchemy_uart_putchar(UART0_PHYS_ADDR, c);
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alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
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}
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@ -66,13 +66,10 @@ void __init board_setup(void)
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au_writel(pin_func, SYS_PINFUNC);
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/* Enable UART */
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au_writel(0x01, UART3_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
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mdelay(10);
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au_writel(0x03, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
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mdelay(10);
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/* Enable DTR = USB power up */
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au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
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alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
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/* Enable DTR (MCR bit 0) = USB power up */
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__raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
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wmb();
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#ifdef CONFIG_PCI
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#if defined(__MIPSEB__)
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@ -59,5 +59,5 @@ void __init prom_init(void)
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void prom_putchar(unsigned char c)
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{
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alchemy_uart_putchar(UART0_PHYS_ADDR, c);
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alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
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}
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@ -3,5 +3,5 @@
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void putc(char c)
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{
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/* all current (Jan. 2010) in-kernel boards */
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alchemy_uart_putchar(UART0_PHYS_ADDR, c);
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alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
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}
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@ -161,6 +161,45 @@ static inline int alchemy_get_cputype(void)
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return ALCHEMY_CPU_UNKNOWN;
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}
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/* return number of uarts on a given cputype */
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static inline int alchemy_get_uarts(int type)
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{
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switch (type) {
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case ALCHEMY_CPU_AU1000:
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return 4;
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case ALCHEMY_CPU_AU1500:
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case ALCHEMY_CPU_AU1200:
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return 2;
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case ALCHEMY_CPU_AU1100:
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case ALCHEMY_CPU_AU1550:
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return 3;
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}
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return 0;
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}
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/* enable an UART block if it isn't already */
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static inline void alchemy_uart_enable(u32 uart_phys)
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{
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void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
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/* reset, enable clock, deassert reset */
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if ((__raw_readl(addr + 0x100) & 3) != 3) {
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__raw_writel(0, addr + 0x100);
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wmb();
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__raw_writel(1, addr + 0x100);
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wmb();
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}
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__raw_writel(3, addr + 0x100);
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wmb();
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}
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static inline void alchemy_uart_disable(u32 uart_phys)
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{
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void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
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__raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */
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wmb();
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}
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static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
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@ -634,6 +673,10 @@ enum soc_au1200_ints {
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*/
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#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
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#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
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#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
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#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
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#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
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#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
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#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
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#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
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@ -660,10 +703,6 @@ enum soc_au1200_ints {
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#define MACDMA0_PHYS_ADDR 0x14004000
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#define MACDMA1_PHYS_ADDR 0x14004200
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#define I2S_PHYS_ADDR 0x11000000
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#define UART0_PHYS_ADDR 0x11100000
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#define UART1_PHYS_ADDR 0x11200000
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#define UART2_PHYS_ADDR 0x11300000
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#define UART3_PHYS_ADDR 0x11400000
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#define SSI0_PHYS_ADDR 0x11600000
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#define SSI1_PHYS_ADDR 0x11680000
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#define SYS_PHYS_ADDR 0x11900000
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@ -695,8 +734,6 @@ enum soc_au1200_ints {
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#define MACDMA0_PHYS_ADDR 0x14004000
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#define MACDMA1_PHYS_ADDR 0x14004200
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#define I2S_PHYS_ADDR 0x11000000
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#define UART0_PHYS_ADDR 0x11100000
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#define UART3_PHYS_ADDR 0x11400000
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#define GPIO2_PHYS_ADDR 0x11700000
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#define SYS_PHYS_ADDR 0x11900000
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#define PCI_MEM_PHYS_ADDR 0x400000000ULL
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@ -732,9 +769,6 @@ enum soc_au1200_ints {
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#define MACDMA0_PHYS_ADDR 0x14004000
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#define MACDMA1_PHYS_ADDR 0x14004200
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#define I2S_PHYS_ADDR 0x11000000
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#define UART0_PHYS_ADDR 0x11100000
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#define UART1_PHYS_ADDR 0x11200000
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#define UART3_PHYS_ADDR 0x11400000
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#define SSI0_PHYS_ADDR 0x11600000
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#define SSI1_PHYS_ADDR 0x11680000
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#define GPIO2_PHYS_ADDR 0x11700000
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@ -758,9 +792,6 @@ enum soc_au1200_ints {
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#define MACEN_PHYS_ADDR 0x10520000
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#define MACDMA0_PHYS_ADDR 0x14004000
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#define MACDMA1_PHYS_ADDR 0x14004200
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#define UART0_PHYS_ADDR 0x11100000
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#define UART1_PHYS_ADDR 0x11200000
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#define UART3_PHYS_ADDR 0x11400000
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#define GPIO2_PHYS_ADDR 0x11700000
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#define SYS_PHYS_ADDR 0x11900000
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#define PE_PHYS_ADDR 0x14008000
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@ -786,8 +817,6 @@ enum soc_au1200_ints {
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#define CIM_PHYS_ADDR 0x14004000
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#define USBM_PHYS_ADDR 0x14020000
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#define USBH_PHYS_ADDR 0x14020100
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#define UART0_PHYS_ADDR 0x11100000
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#define UART1_PHYS_ADDR 0x11200000
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#define GPIO2_PHYS_ADDR 0x11700000
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#define SYS_PHYS_ADDR 0x11900000
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#define PSC0_PHYS_ADDR 0x11A00000
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