redonkable
/
remarkable-linux
1
0
Fork 0
Code Releases Activity

MLK-16028 clk: imx8qm: add clk for dsi0 i2c0 

add clk for dsi0 i2c0

Signed-off-by: Gao Pan <pandy.gao@nxp.com>
pull/10/head
Gao Pan 2017-07-18 13:55:13 +08:00 committed by Jason Liu
parent bc330e9243
commit 80333491f0
3 changed files with 16 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/clk/imx/clk-imx8qm.c
View File

@ -295,7 +295,6 @@ static int imx8qm_clk_probe(struct platform_device *pdev)
/* MIPI -DI SS */
clks[IMX8QM_MIPI0_BYPASS_CLK] = imx_clk_divider_scu("mipi0_bypass_clk", SC_R_MIPI_0, SC_PM_CLK_BYPASS);
clks[IMX8QM_MIPI0_I2C0_DIV] = imx_clk_divider_scu("mipi0_i2c0_div", SC_R_MIPI_0_I2C_0, SC_PM_CLK_PER);
clks[IMX8QM_MIPI0_I2C1_DIV] = imx_clk_divider_scu("mipi0_i2c1_div", SC_R_MIPI_0_I2C_1, SC_PM_CLK_PER);
clks[IMX8QM_MIPI0_PWM0_DIV] = imx_clk_divider_scu("mipi0_pwm0_div", SC_R_MIPI_0_PWM_0, SC_PM_CLK_PER);
clks[IMX8QM_MIPI0_DSI_TX_ESC_DIV] = imx_clk_divider_scu("mipi0_dsi_tx_esc_div", SC_R_MIPI_0, SC_PM_CLK_MST_BUS);
@ -333,6 +332,7 @@ static int imx8qm_clk_probe(struct platform_device *pdev)
clks[IMX8QM_24MHZ] = imx_clk_fixed("xtal_24MHz", 24000000);
clks[IMX8QM_GPT_3M] = imx_clk_fixed("gpt_3m", 3000000);
clks[IMX8QM_32KHZ] = imx_clk_fixed("xtal_32KHz", 32768);
clks[IMX8QM_MIPI0_CLK_ROOT] = imx_clk_fixed("mipi0_clk_root", SC_120MHZ);
/* Conectivity */
clks[IMX8QM_SDHC0_IPG_CLK] = imx_clk_gate2_scu("sdhc0_ipg_clk", "ipg_conn_clk_root", (void __iomem *)(USDHC_0_LPCG), 16, FUNCTION_NAME(PD_CONN_SDHC_0));
@ -682,7 +682,12 @@ static int imx8qm_clk_probe(struct platform_device *pdev)
clks[IMX8QM_HDMI_RX_PXL_ENC_CLK] = imx_clk_gate2_scu("hdmi_rx_sink_enc_clk", "hdmi_rx_pxl_clk", (void __iomem *)(RX_HDMI_LPCG + 0x30), 0, FUNCTION_NAME(PD_HDMI_RX));
/* MIPI-DI */
clks[IMX8QM_MIPI0_I2C0_CLK] = imx_clk_gate_scu("mipi0_i2c0_clk", "mipi0_i2c0_div", SC_R_MIPI_0_I2C_0, SC_PM_CLK_PER, NULL, 0, 0);
clks[IMX8QM_DSI0_LIS_IPG_CLK] = imx_clk_gate2_scu("mipi0_lis_ipg_clk", "mipi0_clk_root", (void __iomem *)(MIPI_DSI_0_LPCG + 0x0), 0, FUNCTION_NAME(PD_MIPI_0_DSI));
clks[IMX8QM_MIPI0_I2C0_DIV] = imx_clk_divider_scu("mipi0_i2c0_div", SC_R_MIPI_0_I2C_0, SC_PM_CLK_MISC2);
clks[IMX8QM_MIPI0_I2C0_CLK] = imx_clk_gate_scu("mipi0_i2c0_clk", "mipi0_i2c0_div", SC_R_MIPI_0_I2C_0, SC_PM_CLK_MISC2, (void __iomem *)(MIPI_DSI_0_LPCG + 0x1c), 0, 0);
clks[IMX8QM_MIPI0_I2C0_IPG_S_CLK] = imx_clk_gate2_scu("mipi0_i2c0_ipg_s", "mipi0_clk_root", (void __iomem *)(MIPI_DSI_0_LPCG + 0x18), 0, FUNCTION_NAME(PD_MIPI_0_DSI_I2C0));
clks[IMX8QM_MIPI0_I2C0_IPG_CLK] = imx_clk_gate2_scu("mipi0_i2c0_ipg", "mipi0_i2c0_ipg_s", (void __iomem *)(MIPI_DSI_0_LPCG + 0x14), 0, FUNCTION_NAME(PD_MIPI_0_DSI_I2C0));
clks[IMX8QM_MIPI0_I2C1_CLK] = imx_clk_gate_scu("mipi0_i2c1_clk", "mipi0_i2c1_div", SC_R_MIPI_0_I2C_1, SC_PM_CLK_PER, NULL, 0, 0);
clks[IMX8QM_MIPI0_PWM0_CLK] = imx_clk_gate_scu("mipi0_pwm0_clk", "mipi0_pwm0_div", SC_R_MIPI_0_PWM_0, SC_PM_CLK_PER, NULL, 0, 0);
clks[IMX8QM_MIPI0_DSI_TX_ESC_CLK] = imx_clk_gate_scu("mipi0_dsi_tx_esc_clk", "mipi0_dsi_tx_esc_div", SC_R_MIPI_0, SC_PM_CLK_MST_BUS, NULL, 0, 0);

6
include/dt-bindings/clock/imx8qm-clock.h
View File

@ -806,7 +806,11 @@
#define IMX8QM_LSIO_MEM_CLK 753
#define IMX8QM_LVDS0_LIS_IPG_CLK 754
#define IMX8QM_LVDS1_LIS_IPG_CLK 755
#define IMX8QM_DSI0_LIS_IPG_CLK 756
#define IMX8QM_MIPI0_I2C0_IPG_S_CLK 757
#define IMX8QM_MIPI0_I2C0_IPG_CLK 758
#define IMX8QM_MIPI0_CLK_ROOT 759
#define IMX8QM_CLK_END 756
#define IMX8QM_CLK_END 760
#endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */

4
include/soc/imx8/imx8qm/lpcg.h
View File

@ -92,6 +92,10 @@
#define MIPI_CSI_0_LPCG 0x58223000
#define MIPI_CSI_1_LPCG 0x58243000
/* MIPI DSI SS */
#define MIPI_DSI_0_LPCG 0x56223000
#define MIPI_DSI_1_LPCG 0x57223000
/* Imaging SS */
#define IMG_JPEG_ENC_LPCG 0x585F0000
#define IMG_JPEG_DEC_LPCG 0x585D0000