nvmem: add i.MX7 support to snvs-lpgpr
The i.MX7 family has similar SNVS hardware so make the snvs-lpgpr support it along with the i.MX6 family. The register interface is the same except for the number and offset of the general purpose registers. Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -1,5 +1,5 @@
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Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
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Secure Non-Volatile Storage.
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and i.MX7 Secure Non-Volatile Storage.
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This DT node should be represented as a sub-node of a "syscon",
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"simple-mfd" node.
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@ -8,6 +8,7 @@ Required properties:
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- compatible: should be one of the fallowing variants:
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"fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
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"fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL
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"fsl,imx7d-snvs-lpgpr" for Freescale i.MX7D/S
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Example:
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snvs: snvs@020cc000 {
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@ -167,10 +167,10 @@ config MESON_MX_EFUSE
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config NVMEM_SNVS_LPGPR
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tristate "Support for Low Power General Purpose Register"
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depends on SOC_IMX6 || COMPILE_TEST
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depends on SOC_IMX6 || SOC_IMX7D || COMPILE_TEST
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help
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This is a driver for Low Power General Purpose Register (LPGPR) available on
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i.MX6 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.
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i.MX6 and i.MX7 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.
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This driver can also be built as a module. If so, the module
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will be called nvmem-snvs-lpgpr.
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@ -14,15 +14,21 @@
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#include <linux/regmap.h>
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#define IMX6Q_SNVS_HPLR 0x00
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#define IMX6Q_GPR_SL BIT(5)
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#define IMX6Q_SNVS_LPLR 0x34
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#define IMX6Q_GPR_HL BIT(5)
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#define IMX6Q_SNVS_LPGPR 0x68
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#define IMX7D_SNVS_HPLR 0x00
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#define IMX7D_SNVS_LPLR 0x34
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#define IMX7D_SNVS_LPGPR 0x90
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#define IMX_GPR_SL BIT(5)
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#define IMX_GPR_HL BIT(5)
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struct snvs_lpgpr_cfg {
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int offset;
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int offset_hplr;
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int offset_lplr;
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int size;
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};
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struct snvs_lpgpr_priv {
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@ -36,6 +42,14 @@ static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = {
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.offset = IMX6Q_SNVS_LPGPR,
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.offset_hplr = IMX6Q_SNVS_HPLR,
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.offset_lplr = IMX6Q_SNVS_LPLR,
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.size = 4,
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};
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static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx7d = {
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.offset = IMX7D_SNVS_LPGPR,
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.offset_hplr = IMX7D_SNVS_HPLR,
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.offset_lplr = IMX7D_SNVS_LPLR,
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.size = 16,
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};
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static int snvs_lpgpr_write(void *context, unsigned int offset, void *val,
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@ -50,14 +64,14 @@ static int snvs_lpgpr_write(void *context, unsigned int offset, void *val,
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if (ret < 0)
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return ret;
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if (lock_reg & IMX6Q_GPR_SL)
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if (lock_reg & IMX_GPR_SL)
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return -EPERM;
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ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg);
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if (ret < 0)
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return ret;
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if (lock_reg & IMX6Q_GPR_HL)
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if (lock_reg & IMX_GPR_HL)
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return -EPERM;
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return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val,
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@ -112,7 +126,7 @@ static int snvs_lpgpr_probe(struct platform_device *pdev)
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cfg->dev = dev;
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cfg->stride = 4;
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cfg->word_size = 4;
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cfg->size = 4;
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cfg->size = dcfg->size,
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cfg->owner = THIS_MODULE;
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cfg->reg_read = snvs_lpgpr_read;
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cfg->reg_write = snvs_lpgpr_write;
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@ -126,6 +140,7 @@ static const struct of_device_id snvs_lpgpr_dt_ids[] = {
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{ .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
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{ .compatible = "fsl,imx6ul-snvs-lpgpr",
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.data = &snvs_lpgpr_cfg_imx6q },
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{ .compatible = "fsl,imx7d-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx7d },
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{ },
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};
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MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids);
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@ -140,5 +155,5 @@ static struct platform_driver snvs_lpgpr_driver = {
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module_platform_driver(snvs_lpgpr_driver);
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MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
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MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 Secure Non-Volatile Storage");
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MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 and i.MX7 Secure Non-Volatile Storage");
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MODULE_LICENSE("GPL v2");
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