[ARM] 4440/1: PXA: enable the checking of ICIP2 for IRQs
ICIP2 is not examined during IRQ entrance, this patch add the checking if the processor is PXA27x or later, with CoreG bits in CPUID (Core Generation) > 1 Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -20,15 +20,33 @@
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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#ifdef CONFIG_PXA27x
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mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
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mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
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#else
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mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
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mov \tmp, \tmp, lsr #13
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and \tmp, \tmp, #0x7 @ Core G
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cmp \tmp, #1
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bhi 1004f
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mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
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add \base, \base, #0x00d00000
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ldr \irqstat, [\base, #0] @ ICIP
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ldr \irqnr, [\base, #4] @ ICMR
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#endif
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b 1002f
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1004:
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mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2
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mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2
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ands \irqstat, \irqstat, \irqnr
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beq 1003f
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rsb \irqstat, \irqnr, #0
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and \irqstat, \irqstat, \irqnr
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clz \irqnr, \irqstat
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rsb \irqnr, \irqnr, #31
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add \irqnr, \irqnr, #32
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b 1001f
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1003:
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mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
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mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
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1002:
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ands \irqnr, \irqstat, \irqnr
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beq 1001f
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rsb \irqstat, \irqnr, #0
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