Merge branch 'i2c-for-2630-rc5' of git://aeryn.fluff.org.uk/bjdooks/linux
* 'i2c-for-2630-rc5' of git://aeryn.fluff.org.uk/bjdooks/linux: i2c-cpm: Pass dev ptr to dma_*_coherent rather than NULL i2c: Enable i2c-s3c2410 for S3C64XX too i2c-mpc: bug fix for MPC52xx clock setting and printout i2c-pxa.c: timeouts off by 1
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commit
816dc3c82b
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@ -467,7 +467,7 @@ config I2C_PXA_SLAVE
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config I2C_S3C2410
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tristate "S3C2410 I2C Driver"
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depends on ARCH_S3C2410
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depends on ARCH_S3C2410 || ARCH_S3C64XX
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help
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Say Y here to include support for I2C controller in the
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Samsung S3C2410 based System-on-Chip devices.
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@ -531,16 +531,16 @@ static int __devinit cpm_i2c_setup(struct cpm_i2c *cpm)
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rbdf = cpm->rbase;
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for (i = 0; i < CPM_MAXBD; i++) {
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cpm->rxbuf[i] = dma_alloc_coherent(
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NULL, CPM_MAX_READ + 1, &cpm->rxdma[i], GFP_KERNEL);
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cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
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CPM_MAX_READ + 1,
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&cpm->rxdma[i], GFP_KERNEL);
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if (!cpm->rxbuf[i]) {
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ret = -ENOMEM;
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goto out_muram;
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}
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out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
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cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(
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NULL, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
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cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
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if (!cpm->txbuf[i]) {
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ret = -ENOMEM;
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goto out_muram;
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@ -585,10 +585,10 @@ static int __devinit cpm_i2c_setup(struct cpm_i2c *cpm)
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out_muram:
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for (i = 0; i < CPM_MAXBD; i++) {
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if (cpm->rxbuf[i])
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dma_free_coherent(NULL, CPM_MAX_READ + 1,
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dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
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cpm->rxbuf[i], cpm->rxdma[i]);
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if (cpm->txbuf[i])
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dma_free_coherent(NULL, CPM_MAX_READ + 1,
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dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
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cpm->txbuf[i], cpm->txdma[i]);
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}
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cpm_muram_free(cpm->dp_addr);
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@ -619,9 +619,9 @@ static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
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/* Free all memory */
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for (i = 0; i < CPM_MAXBD; i++) {
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dma_free_coherent(NULL, CPM_MAX_READ + 1,
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dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
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cpm->rxbuf[i], cpm->rxdma[i]);
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dma_free_coherent(NULL, CPM_MAX_READ + 1,
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dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
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cpm->txbuf[i], cpm->txdma[i]);
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}
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@ -164,7 +164,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
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return 0;
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}
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#ifdef CONFIG_PPC_52xx
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#ifdef CONFIG_PPC_MPC52xx
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static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
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{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
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{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
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@ -188,7 +188,7 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
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int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
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{
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const struct mpc52xx_i2c_divider *div = NULL;
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const struct mpc_i2c_divider *div = NULL;
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unsigned int pvr = mfspr(SPRN_PVR);
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u32 divider;
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int i;
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@ -203,7 +203,7 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
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* We want to choose an FDR/DFSR that generates an I2C bus speed that
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* is equal to or lower than the requested speed.
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*/
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for (i = 0; i < ARRAY_SIZE(mpc52xx_i2c_dividers); i++) {
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for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
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div = &mpc_i2c_dividers_52xx[i];
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/* Old MPC5200 rev A CPUs do not support the high bits */
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if (div->fdr & 0xc0 && pvr == 0x80822011)
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@ -219,20 +219,23 @@ static void mpc_i2c_setclock_52xx(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock, u32 prescaler)
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{
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int fdr = mpc52xx_i2c_get_fdr(node, clock, prescaler);
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int ret, fdr;
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ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
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fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
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if (fdr < 0)
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fdr = 0x3f; /* backward compatibility */
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writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
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dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
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if (ret >= 0)
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dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
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}
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#else /* !CONFIG_PPC_52xx */
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#else /* !CONFIG_PPC_MPC52xx */
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static void mpc_i2c_setclock_52xx(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock, u32 prescaler)
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{
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}
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#endif /* CONFIG_PPC_52xx*/
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#endif /* CONFIG_PPC_MPC52xx*/
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#ifdef CONFIG_FSL_SOC
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static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
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struct mpc_i2c *i2c,
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u32 clock, u32 prescaler)
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{
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int fdr = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
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int ret, fdr;
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ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
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fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
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if (fdr < 0)
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fdr = 0x1031; /* backward compatibility */
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writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
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writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
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dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
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clock, fdr >> 8, fdr & 0xff);
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if (ret >= 0)
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dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
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clock, fdr >> 8, fdr & 0xff);
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}
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#else /* !CONFIG_FSL_SOC */
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@ -265,10 +265,10 @@ static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
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show_state(i2c);
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}
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if (timeout <= 0)
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if (timeout < 0)
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show_state(i2c);
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return timeout <= 0 ? I2C_RETRY : 0;
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return timeout < 0 ? I2C_RETRY : 0;
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}
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static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
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show_state(i2c);
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}
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if (timeout <= 0) {
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if (timeout < 0) {
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show_state(i2c);
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dev_err(&i2c->adap.dev,
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"i2c_pxa: timeout waiting for bus free\n");
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