[libata] pata_bf54x: Support sg list in bmdma transfer.
BF54x on-chip ATAPI controller allows maximum 0x1fffe bytes to be transfered in one ATAPI transfer. So, set the max sg_tablesize to 4. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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@ -251,6 +251,8 @@ static const u32 udma_tenvmin = 20;
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static const u32 udma_tackmin = 20;
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static const u32 udma_tssmin = 50;
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#define BFIN_MAX_SG_SEGMENTS 4
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/**
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*
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* Function: num_clocks_min
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@ -829,30 +831,74 @@ static void bfin_set_devctl(struct ata_port *ap, u8 ctl)
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static void bfin_bmdma_setup(struct ata_queued_cmd *qc)
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{
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unsigned short config = WDSIZE_16;
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struct ata_port *ap = qc->ap;
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struct dma_desc_array *dma_desc_cpu = (struct dma_desc_array *)ap->bmdma_prd;
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void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
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unsigned short config = DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_16 | DMAEN;
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struct scatterlist *sg;
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unsigned int si;
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unsigned int channel;
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unsigned int dir;
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unsigned int size = 0;
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dev_dbg(qc->ap->dev, "in atapi dma setup\n");
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/* Program the ATA_CTRL register with dir */
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if (qc->tf.flags & ATA_TFLAG_WRITE) {
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/* fill the ATAPI DMA controller */
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set_dma_config(CH_ATAPI_TX, config);
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set_dma_x_modify(CH_ATAPI_TX, 2);
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for_each_sg(qc->sg, sg, qc->n_elem, si) {
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set_dma_start_addr(CH_ATAPI_TX, sg_dma_address(sg));
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set_dma_x_count(CH_ATAPI_TX, sg_dma_len(sg) >> 1);
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}
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channel = CH_ATAPI_TX;
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dir = DMA_TO_DEVICE;
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} else {
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channel = CH_ATAPI_RX;
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dir = DMA_FROM_DEVICE;
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config |= WNR;
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}
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dma_map_sg(ap->dev, qc->sg, qc->n_elem, dir);
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/* fill the ATAPI DMA controller */
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set_dma_config(CH_ATAPI_RX, config);
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set_dma_x_modify(CH_ATAPI_RX, 2);
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for_each_sg(qc->sg, sg, qc->n_elem, si) {
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set_dma_start_addr(CH_ATAPI_RX, sg_dma_address(sg));
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set_dma_x_count(CH_ATAPI_RX, sg_dma_len(sg) >> 1);
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dma_desc_cpu[si].start_addr = sg_dma_address(sg);
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dma_desc_cpu[si].cfg = config;
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dma_desc_cpu[si].x_count = sg_dma_len(sg) >> 1;
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dma_desc_cpu[si].x_modify = 2;
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size += sg_dma_len(sg);
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}
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/* Set the last descriptor to stop mode */
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dma_desc_cpu[qc->n_elem - 1].cfg &= ~(DMAFLOW | NDSIZE);
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flush_dcache_range((unsigned int)dma_desc_cpu,
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(unsigned int)dma_desc_cpu +
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qc->n_elem * sizeof(struct dma_desc_array));
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/* Enable ATA DMA operation*/
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set_dma_curr_desc_addr(channel, (unsigned long *)ap->bmdma_prd_dma);
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set_dma_x_count(channel, 0);
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set_dma_x_modify(channel, 0);
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set_dma_config(channel, config);
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SSYNC();
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/* Send ATA DMA command */
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bfin_exec_command(ap, &qc->tf);
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if (qc->tf.flags & ATA_TFLAG_WRITE) {
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/* set ATA DMA write direction */
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ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
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| XFER_DIR));
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} else {
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/* set ATA DMA read direction */
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ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
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& ~XFER_DIR));
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}
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/* Reset all transfer count */
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ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST);
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/* Set ATAPI state machine contorl in terminate sequence */
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ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM);
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/* Set transfer length to the total size of sg buffers */
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ATAPI_SET_XFER_LEN(base, size >> 1);
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}
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/**
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@ -866,59 +912,13 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
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struct scatterlist *sg;
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unsigned int si;
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dev_dbg(qc->ap->dev, "in atapi dma start\n");
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if (!(ap->udma_mask || ap->mwdma_mask))
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return;
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/* start ATAPI DMA controller*/
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if (qc->tf.flags & ATA_TFLAG_WRITE) {
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/*
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* On blackfin arch, uncacheable memory is not
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* allocated with flag GFP_DMA. DMA buffer from
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* common kenel code should be flushed if WB
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* data cache is enabled. Otherwise, this loop
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* is an empty loop and optimized out.
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*/
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for_each_sg(qc->sg, sg, qc->n_elem, si) {
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flush_dcache_range(sg_dma_address(sg),
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sg_dma_address(sg) + sg_dma_len(sg));
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}
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enable_dma(CH_ATAPI_TX);
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dev_dbg(qc->ap->dev, "enable udma write\n");
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/* Send ATA DMA write command */
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bfin_exec_command(ap, &qc->tf);
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/* set ATA DMA write direction */
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ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
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| XFER_DIR));
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} else {
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enable_dma(CH_ATAPI_RX);
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dev_dbg(qc->ap->dev, "enable udma read\n");
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/* Send ATA DMA read command */
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bfin_exec_command(ap, &qc->tf);
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/* set ATA DMA read direction */
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ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
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& ~XFER_DIR));
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}
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/* Reset all transfer count */
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ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST);
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/* Set ATAPI state machine contorl in terminate sequence */
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ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM);
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/* Set transfer length to buffer len */
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for_each_sg(qc->sg, sg, qc->n_elem, si) {
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ATAPI_SET_XFER_LEN(base, (sg_dma_len(sg) >> 1));
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}
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/* Enable ATA DMA operation*/
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/* start ATAPI transfer*/
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if (ap->udma_mask)
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ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
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| ULTRA_START);
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@ -935,34 +935,23 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc)
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static void bfin_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct scatterlist *sg;
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unsigned int si;
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unsigned int dir;
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dev_dbg(qc->ap->dev, "in atapi dma stop\n");
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if (!(ap->udma_mask || ap->mwdma_mask))
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return;
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/* stop ATAPI DMA controller*/
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if (qc->tf.flags & ATA_TFLAG_WRITE)
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if (qc->tf.flags & ATA_TFLAG_WRITE) {
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dir = DMA_TO_DEVICE;
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disable_dma(CH_ATAPI_TX);
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else {
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} else {
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dir = DMA_FROM_DEVICE;
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disable_dma(CH_ATAPI_RX);
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if (ap->hsm_task_state & HSM_ST_LAST) {
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/*
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* On blackfin arch, uncacheable memory is not
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* allocated with flag GFP_DMA. DMA buffer from
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* common kenel code should be invalidated if
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* data cache is enabled. Otherwise, this loop
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* is an empty loop and optimized out.
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*/
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for_each_sg(qc->sg, sg, qc->n_elem, si) {
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invalidate_dcache_range(
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sg_dma_address(sg),
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sg_dma_address(sg)
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+ sg_dma_len(sg));
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}
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}
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}
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dma_unmap_sg(ap->dev, qc->sg, qc->n_elem, dir);
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}
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/**
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@ -1260,6 +1249,11 @@ static void bfin_port_stop(struct ata_port *ap)
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{
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dev_dbg(ap->dev, "in atapi port stop\n");
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if (ap->udma_mask != 0 || ap->mwdma_mask != 0) {
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dma_free_coherent(ap->dev,
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BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array),
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ap->bmdma_prd,
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ap->bmdma_prd_dma);
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free_dma(CH_ATAPI_RX);
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free_dma(CH_ATAPI_TX);
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}
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@ -1271,14 +1265,29 @@ static int bfin_port_start(struct ata_port *ap)
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if (!(ap->udma_mask || ap->mwdma_mask))
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return 0;
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ap->bmdma_prd = dma_alloc_coherent(ap->dev,
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BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array),
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&ap->bmdma_prd_dma,
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GFP_KERNEL);
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if (ap->bmdma_prd == NULL) {
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dev_info(ap->dev, "Unable to allocate DMA descriptor array.\n");
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goto out;
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}
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if (request_dma(CH_ATAPI_RX, "BFIN ATAPI RX DMA") >= 0) {
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if (request_dma(CH_ATAPI_TX,
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"BFIN ATAPI TX DMA") >= 0)
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return 0;
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free_dma(CH_ATAPI_RX);
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dma_free_coherent(ap->dev,
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BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array),
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ap->bmdma_prd,
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ap->bmdma_prd_dma);
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}
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out:
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ap->udma_mask = 0;
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ap->mwdma_mask = 0;
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dev_err(ap->dev, "Unable to request ATAPI DMA!"
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@ -1400,7 +1409,7 @@ static irqreturn_t bfin_ata_interrupt(int irq, void *dev_instance)
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static struct scsi_host_template bfin_sht = {
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ATA_BASE_SHT(DRV_NAME),
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.sg_tablesize = SG_NONE,
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.sg_tablesize = BFIN_MAX_SG_SEGMENTS,
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.dma_boundary = ATA_DMA_BOUNDARY,
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};
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