MLK-17491-35 clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and denominator value in register are start from 0. This can be used to support frac dividers like below: Divider output clock = Divider input clock x [(frac +1) / (div +1)] where frac/div in register is: 000b - Divide by 1. 001b - Divide by 2. 010b - Divide by 3. Cc: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>pull/10/head
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3213cec014
commit
8348172898
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@ -40,6 +40,11 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
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m = (val & fd->mmask) >> fd->mshift;
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n = (val & fd->nmask) >> fd->nshift;
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if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
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m++;
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n++;
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}
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if (!n || !m)
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return parent_rate;
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@ -103,6 +108,11 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
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GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
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&m, &n);
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if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
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m--;
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n--;
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}
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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else
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@ -565,6 +565,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
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* @lock: register lock
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*
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* Clock with adjustable fractional divider affecting its output frequency.
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*
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* Flags:
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* CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
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* is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
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* is set then the numerator and denominator are both the value read
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* plus one.
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*/
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struct clk_fractional_divider {
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struct clk_hw hw;
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@ -584,6 +590,8 @@ struct clk_fractional_divider {
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#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
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#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
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extern const struct clk_ops clk_fractional_divider_ops;
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struct clk *clk_register_fractional_divider(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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