Opteron revision F will support higher frequencies than
can be encoded in the current driver's 4 bit frequency field. This patch updates the driver to support Rev F including 6 bit FIDs and processor ID updates. This should apply cleanly whether or not the dual-core bugfix I sent out last week is applied. I'd prefer that both get applied, of course. Signed-off-by: David Keck <david.keck@amd.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com> Signed-off-by: Dave Jones <davej@redhat.com>wifi-calibration
Dave Jones
parent
03938c3f10
commit
841e40b380
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@ -1,5 +1,5 @@
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/*
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* (c) 2003, 2004 Advanced Micro Devices, Inc.
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* (c) 2003, 2004, 2005 Advanced Micro Devices, Inc.
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* Your use of this code is subject to the terms and conditions of the
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* GNU general public license version 2. See "COPYING" or
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* http://www.gnu.org/licenses/gpl.html
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@ -44,7 +44,7 @@
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#define PFX "powernow-k8: "
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#define BFX PFX "BIOS error: "
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#define VERSION "version 1.40.4"
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#define VERSION "version 1.50.3"
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#include "powernow-k8.h"
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/* serialize freq changes */
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@ -232,7 +232,7 @@ static int write_new_vid(struct powernow_k8_data *data, u32 vid)
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/*
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* Reduce the vid by the max of step or reqvid.
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* Decreasing vid codes represent increasing voltages:
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* vid of 0 is 1.550V, vid of 0x1e is 0.800V, vid of 0x1f is off.
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* vid of 0 is 1.550V, vid of 0x1e is 0.800V, vid of VID_OFF is off.
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*/
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static int decrease_vid_code_by_step(struct powernow_k8_data *data, u32 reqvid, u32 step)
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{
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@ -467,7 +467,7 @@ static int check_supported_cpu(unsigned int cpu)
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eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
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if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) ||
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((eax & CPUID_XFAM) != CPUID_XFAM_K8) ||
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((eax & CPUID_XMOD) > CPUID_XMOD_REV_E)) {
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((eax & CPUID_XMOD) > CPUID_XMOD_REV_F)) {
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printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax);
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goto out;
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}
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@ -696,6 +696,7 @@ static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned
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data->irt = (data->acpi_data.states[index].control >> IRT_SHIFT) & IRT_MASK;
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data->rvo = (data->acpi_data.states[index].control >> RVO_SHIFT) & RVO_MASK;
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data->exttype = (data->acpi_data.states[index].control >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK;
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data->plllock = (data->acpi_data.states[index].control >> PLL_L_SHIFT) & PLL_L_MASK;
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data->vidmvs = 1 << ((data->acpi_data.states[index].control >> MVS_SHIFT) & MVS_MASK);
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data->vstable = (data->acpi_data.states[index].control >> VST_SHIFT) & VST_MASK;
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@ -735,8 +736,13 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
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}
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for (i = 0; i < data->acpi_data.state_count; i++) {
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u32 fid = data->acpi_data.states[i].control & FID_MASK;
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u32 vid = (data->acpi_data.states[i].control >> VID_SHIFT) & VID_MASK;
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if (data->exttype) {
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u32 fid = data->acpi_data.states[i].status & FID_MASK;
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u32 vid = (data->acpi_data.states[i].status >> VID_SHIFT) & VID_MASK;
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} else {
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u32 fid = data->acpi_data.states[i].control & FID_MASK;
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u32 vid = (data->acpi_data.states[i].control >> VID_SHIFT) & VID_MASK;
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}
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dprintk(" %d : fid 0x%x, vid 0x%x\n", i, fid, vid);
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@ -753,7 +759,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
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}
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/* verify voltage is OK - BIOSs are using "off" to indicate invalid */
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if (vid == 0x1f) {
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if (vid == VID_OFF) {
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dprintk("invalid vid %u, ignoring\n", vid);
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powernow_table[i].frequency = CPUFREQ_ENTRY_INVALID;
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continue;
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@ -930,15 +936,6 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
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down(&fidvid_sem);
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for_each_cpu_mask(i, cpu_core_map[pol->cpu]) {
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/* make sure the sibling is initialized */
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if (!powernow_data[i]) {
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ret = 0;
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up(&fidvid_sem);
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goto err_out;
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}
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}
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powernow_k8_acpi_pst_values(data, newstate);
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if (transition_frequency(data, newstate)) {
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@ -1,5 +1,5 @@
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/*
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* (c) 2003, 2004 Advanced Micro Devices, Inc.
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* (c) 2003, 2004, 2005 Advanced Micro Devices, Inc.
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* Your use of this code is subject to the terms and conditions of the
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* GNU general public license version 2. See "COPYING" or
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* http://www.gnu.org/licenses/gpl.html
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@ -19,6 +19,7 @@ struct powernow_k8_data {
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u32 vidmvs; /* usable value calculated from mvs */
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u32 vstable; /* voltage stabilization time, units 20 us */
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u32 plllock; /* pll lock time, units 1 us */
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u32 exttype; /* extended interface = 1 */
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/* keep track of the current fid / vid */
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u32 currvid, currfid;
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@ -41,7 +42,7 @@ struct powernow_k8_data {
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#define CPUID_XFAM 0x0ff00000 /* extended family */
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#define CPUID_XFAM_K8 0
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#define CPUID_XMOD 0x000f0000 /* extended model */
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#define CPUID_XMOD_REV_E 0x00020000
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#define CPUID_XMOD_REV_F 0x00040000
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#define CPUID_USE_XFAM_XMOD 0x00000f00
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#define CPUID_GET_MAX_CAPABILITIES 0x80000000
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#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
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@ -57,25 +58,26 @@ struct powernow_k8_data {
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/* Field definitions within the FID VID Low Control MSR : */
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#define MSR_C_LO_INIT_FID_VID 0x00010000
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#define MSR_C_LO_NEW_VID 0x00001f00
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#define MSR_C_LO_NEW_FID 0x0000002f
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#define MSR_C_LO_NEW_VID 0x00003f00
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#define MSR_C_LO_NEW_FID 0x0000003f
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#define MSR_C_LO_VID_SHIFT 8
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/* Field definitions within the FID VID High Control MSR : */
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#define MSR_C_HI_STP_GNT_TO 0x000fffff
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#define MSR_C_HI_STP_GNT_TO 0x000fffff
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/* Field definitions within the FID VID Low Status MSR : */
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#define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
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#define MSR_S_LO_MAX_RAMP_VID 0x1f000000
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#define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
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#define MSR_S_LO_MAX_RAMP_VID 0x3f000000
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#define MSR_S_LO_MAX_FID 0x003f0000
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#define MSR_S_LO_START_FID 0x00003f00
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#define MSR_S_LO_CURRENT_FID 0x0000003f
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/* Field definitions within the FID VID High Status MSR : */
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#define MSR_S_HI_MAX_WORKING_VID 0x001f0000
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#define MSR_S_HI_START_VID 0x00001f00
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#define MSR_S_HI_CURRENT_VID 0x0000001f
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#define MSR_C_HI_STP_GNT_BENIGN 0x00000001
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#define MSR_S_HI_MIN_WORKING_VID 0x3f000000
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#define MSR_S_HI_MAX_WORKING_VID 0x003f0000
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#define MSR_S_HI_START_VID 0x00003f00
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#define MSR_S_HI_CURRENT_VID 0x0000003f
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#define MSR_C_HI_STP_GNT_BENIGN 0x00000001
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/*
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* There are restrictions frequencies have to follow:
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@ -99,13 +101,15 @@ struct powernow_k8_data {
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#define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */
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#define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */
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#define LEAST_VID 0x1e /* Lowest (numerically highest) useful vid value */
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#define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */
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#define MIN_FREQ 800 /* Min and max freqs, per spec */
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#define MAX_FREQ 5000
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#define INVALID_FID_MASK 0xffffffc1 /* not a valid fid if these bits are set */
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#define INVALID_VID_MASK 0xffffffe0 /* not a valid vid if these bits are set */
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#define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */
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#define VID_OFF 0x3f
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#define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
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Reference in New Issue