MIPS: Emulate the new MIPS R6 BALC instruction
MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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@ -33,7 +33,7 @@ enum major_op {
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sdl_op, sdr_op, swr_op, cache_op,
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ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
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lld_op, ldc1_op, ldc2_op, ld_op,
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sc_op, swc1_op, swc2_op, major_3b_op,
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sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
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scd_op, sdc1_op, sdc2_op, sd_op
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};
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@ -789,6 +789,16 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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}
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regs->cp0_epc += 8;
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break;
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case balc6_op:
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if (!cpu_has_mips_r6) {
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ret = -SIGILL;
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break;
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}
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/* Compact branch: BALC */
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regs->regs[31] = epc + 4;
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epc += 4 + (insn.i_format.simmediate << 2);
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regs->cp0_epc = epc;
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break;
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#endif
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case cbcond0_op:
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case cbcond1_op:
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@ -670,6 +670,14 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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*contpc = regs->cp0_epc + dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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case balc6_op:
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if (!cpu_has_mips_r6)
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break;
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regs->regs[31] = regs->cp0_epc + 4;
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*contpc = regs->cp0_epc + dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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#endif
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case cop0_op:
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