intel_agp,i915: Add more sandybridge graphics device ids
New pci ids for GT2 and GT2+ on desktop and mobile sandybridge, and graphics device ids for server sandybridge. Also rename original ids string to reflect GT1 version. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -816,11 +816,19 @@ static const struct intel_driver_description {
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"HD Graphics", NULL, &intel_i965_driver },
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{ PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
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"HD Graphics", NULL, &intel_i965_driver },
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{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG,
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{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
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"Sandybridge", NULL, &intel_gen6_driver },
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{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG,
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{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
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"Sandybridge", NULL, &intel_gen6_driver },
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{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_D0_IG,
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{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
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"Sandybridge", NULL, &intel_gen6_driver },
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{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
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"Sandybridge", NULL, &intel_gen6_driver },
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{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
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"Sandybridge", NULL, &intel_gen6_driver },
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{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
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"Sandybridge", NULL, &intel_gen6_driver },
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{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
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"Sandybridge", NULL, &intel_gen6_driver },
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{ 0, 0, NULL, NULL, NULL }
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};
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@ -1045,6 +1053,7 @@ static struct pci_device_id agp_intel_pci_table[] = {
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
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ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
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ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
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ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),
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{ }
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};
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@ -202,11 +202,16 @@
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG 0x0106
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_D0_IG 0x0126
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 /* Desktop */
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG 0x0102
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG 0x0112
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG 0x0122
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Mobile */
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG 0x0106
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG 0x0116
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
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/* cover 915 and 945 variants */
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#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
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@ -233,7 +238,8 @@
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
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#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB)
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#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
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@ -618,8 +618,7 @@ static void intel_i830_init_gtt_entries(void)
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gtt_entries = 0;
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break;
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}
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} else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) {
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} else if (IS_SNB) {
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/*
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* SandyBridge has new memory control reg at 0x50.w
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*/
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@ -1389,6 +1388,7 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
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break;
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case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
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case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
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case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB:
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*gtt_offset = MB(2);
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pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
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@ -175,8 +175,12 @@ static const struct pci_device_id pciidlist[] = { /* aka */
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INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
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INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
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INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
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{0, 0, 0}
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};
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