[ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created
This patch adds a workaround for the 458693 Cortex-A8 (r2p0) erratum. It sets the corresponding bits in the auxiliary control register so that the PLD instruction becomes a NOP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -765,6 +765,19 @@ config ARM_ERRATA_430973
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Note that setting specific bits in the ACTLR register may not be
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available in non-secure mode.
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config ARM_ERRATA_458693
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bool "ARM errata: Processor deadlock when a false hazard is created"
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depends on CPU_V7
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help
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This option enables the workaround for the 458693 Cortex-A8 (r2p0)
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erratum. For very specific sequences of memory operations, it is
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possible for a hazard condition intended for a cache line to instead
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be incorrectly associated with a different cache line. This false
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hazard might then cause a processor deadlock. The workaround enables
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the L1 caching of the NEON accesses and disables the PLD instruction
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in the ACTLR register. Note that setting specific bits in the ACTLR
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register may not be available in non-secure mode.
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endmenu
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source "arch/arm/common/Kconfig"
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@ -187,6 +187,12 @@ __v7_setup:
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mrc p15, 0, r10, c1, c0, 1 @ read aux control register
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orr r10, r10, #(1 << 6) @ set IBE to 1
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mcr p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_458693
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mrc p15, 0, r10, c1, c0, 1 @ read aux control register
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orr r10, r10, #(1 << 5) @ set L1NEON to 1
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orr r10, r10, #(1 << 9) @ set PLDNOP to 1
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mcr p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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mov r10, #0
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#ifdef HARVARD_CACHE
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