powerpc/mm: Use read barrier when creating real_pte
On ppc64 we support 4K hash pte with 64K page size. That requires us to track the hash pte slot information on a per 4k basis. We do that by storing the slot details in the second half of pte page. The pte bit _PAGE_COMBO is used to indicate whether the second half need to be looked while building real_pte. We need to use read memory barrier while doing that so that load of hidx is not reordered w.r.t _PAGE_COMBO check. On the store side we already do a lwsync in __hash_page_4K CC: <stable@vger.kernel.org> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -46,11 +46,31 @@
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* in order to deal with 64K made of 4K HW pages. Thus we override the
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* in order to deal with 64K made of 4K HW pages. Thus we override the
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* generic accessors and iterators here
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* generic accessors and iterators here
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*/
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*/
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#define __real_pte(e,p) ((real_pte_t) { \
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#define __real_pte __real_pte
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(e), (pte_val(e) & _PAGE_COMBO) ? \
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static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep)
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(pte_val(*((p) + PTRS_PER_PTE))) : 0 })
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{
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#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
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real_pte_t rpte;
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(((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
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rpte.pte = pte;
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rpte.hidx = 0;
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if (pte_val(pte) & _PAGE_COMBO) {
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/*
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* Make sure we order the hidx load against the _PAGE_COMBO
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* check. The store side ordering is done in __hash_page_4K
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*/
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smp_rmb();
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rpte.hidx = pte_val(*((ptep) + PTRS_PER_PTE));
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}
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return rpte;
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}
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static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
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{
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if ((pte_val(rpte.pte) & _PAGE_COMBO))
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return (rpte.hidx >> (index<<2)) & 0xf;
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return (pte_val(rpte.pte) >> 12) & 0xf;
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}
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#define __rpte_to_pte(r) ((r).pte)
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#define __rpte_to_pte(r) ((r).pte)
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#define __rpte_sub_valid(rpte, index) \
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#define __rpte_sub_valid(rpte, index) \
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(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
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(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
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