drm/i915: Make IS_BROADWELL only take dev_priv
Saves 1808 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
This commit is contained in:
parent
fd6b8f43c9
commit
8652744b64
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@ -189,13 +189,15 @@ static void intel_detect_pch(struct drm_device *dev)
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} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
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dev_priv->pch_type = PCH_LPT;
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DRM_DEBUG_KMS("Found LynxPoint PCH\n");
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WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
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WARN_ON(!IS_HASWELL(dev_priv) &&
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!IS_BROADWELL(dev_priv));
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WARN_ON(IS_HSW_ULT(dev_priv) ||
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IS_BDW_ULT(dev_priv));
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} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
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dev_priv->pch_type = PCH_LPT;
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DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
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WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
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WARN_ON(!IS_HASWELL(dev_priv) &&
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!IS_BROADWELL(dev_priv));
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WARN_ON(!IS_HSW_ULT(dev_priv) &&
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!IS_BDW_ULT(dev_priv));
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} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
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@ -2658,7 +2658,7 @@ struct drm_i915_cmd_table {
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#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
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#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
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#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
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#define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
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#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
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#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
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#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
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#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
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@ -2765,8 +2765,8 @@ struct drm_i915_cmd_table {
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#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
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#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
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#define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
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#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
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HAS_EDRAM(dev))
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#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
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IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
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#define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
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#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
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@ -3480,7 +3480,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
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level = I915_CACHE_LLC;
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break;
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case I915_CACHING_DISPLAY:
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level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
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level = HAS_WT(dev_priv) ? I915_CACHE_WT : I915_CACHE_NONE;
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break;
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default:
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return -EINVAL;
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@ -3538,7 +3538,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
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* with that bit in the PTE to main memory with just one PIPE_CONTROL.
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*/
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ret = i915_gem_object_set_cache_level(obj,
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HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
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HAS_WT(to_i915(obj->base.dev)) ?
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I915_CACHE_WT : I915_CACHE_NONE);
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if (ret) {
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vma = ERR_PTR(ret);
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goto err_unpin_display;
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@ -2131,7 +2131,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
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* workarounds here even if they get overwritten by GPU reset.
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*/
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/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
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if (IS_BROADWELL(dev))
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if (IS_BROADWELL(dev_priv))
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I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
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else if (IS_CHERRYVIEW(dev))
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I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
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@ -540,8 +540,8 @@ void intel_color_init(struct drm_crtc *crtc)
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} else if (IS_HASWELL(dev)) {
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dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
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dev_priv->display.load_luts = haswell_load_luts;
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} else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) ||
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IS_BROXTON(dev) || IS_KABYLAKE(dev)) {
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} else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
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IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) {
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dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
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dev_priv->display.load_luts = broadwell_load_luts;
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} else {
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@ -3139,7 +3139,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
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dspcntr = DISPPLANE_GAMMA_ENABLE;
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dspcntr |= DISPLAY_PLANE_ENABLE;
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
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switch (fb->pixel_format) {
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@ -3168,7 +3168,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
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if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
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dspcntr |= DISPPLANE_TILED;
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if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
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if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
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dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
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intel_add_fb_offsets(&x, &y, plane_state, 0);
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@ -3179,7 +3179,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
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if (rotation == DRM_ROTATE_180) {
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dspcntr |= DISPPLANE_ROTATE_180;
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if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
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if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
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x += (crtc_state->pipe_src_w - 1);
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y += (crtc_state->pipe_src_h - 1);
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}
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@ -3196,7 +3196,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
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I915_WRITE(DSPSURF(plane),
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intel_fb_gtt_offset(fb, rotation) +
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intel_crtc->dspaddr_offset);
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if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
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} else {
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I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
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@ -4877,7 +4877,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
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*/
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assert_plane_enabled(dev_priv, crtc->plane);
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if (IS_BROADWELL(dev)) {
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if (IS_BROADWELL(dev_priv)) {
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mutex_lock(&dev_priv->rps.hw_lock);
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WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
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mutex_unlock(&dev_priv->rps.hw_lock);
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@ -4909,7 +4909,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
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return;
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assert_plane_enabled(dev_priv, crtc->plane);
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if (IS_BROADWELL(dev)) {
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if (IS_BROADWELL(dev_priv)) {
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mutex_lock(&dev_priv->rps.hw_lock);
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WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
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mutex_unlock(&dev_priv->rps.hw_lock);
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@ -5852,7 +5852,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
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dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
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} else if (IS_BROXTON(dev)) {
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dev_priv->max_cdclk_freq = 624000;
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} else if (IS_BROADWELL(dev)) {
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} else if (IS_BROADWELL(dev_priv)) {
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/*
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* FIXME with extra cooling we can allow
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* 540 MHz for ULX and 675 Mhz for ULT.
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@ -7021,6 +7021,7 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
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static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_atomic_state *state = pipe_config->base.state;
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struct intel_crtc *other_crtc;
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struct intel_crtc_state *other_crtc_state;
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@ -7033,7 +7034,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
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return -EINVAL;
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}
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if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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if (pipe_config->fdi_lanes > 2) {
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DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
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pipe_config->fdi_lanes);
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@ -9881,7 +9882,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
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fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
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base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
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if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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offset = I915_READ(DSPOFFSET(pipe));
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} else {
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if (plane_config->tiling)
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@ -17244,7 +17245,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
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return;
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err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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err_printf(m, "PWR_WELL_CTL2: %08x\n",
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error->power_well_driver);
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for_each_pipe(dev_priv, i) {
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@ -821,15 +821,16 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
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uint32_t aux_clock_divider)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = intel_dig_port->base.base.dev;
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struct drm_i915_private *dev_priv =
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to_i915(intel_dig_port->base.base.dev);
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uint32_t precharge, timeout;
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if (IS_GEN6(dev))
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if (IS_GEN6(dev_priv))
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precharge = 3;
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else
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precharge = 5;
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if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
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if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
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timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
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else
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timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
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@ -2999,10 +3000,10 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
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uint8_t
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intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
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enum port port = dp_to_dig_port(intel_dp)->port;
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if (INTEL_INFO(dev)->gen >= 9) {
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if (INTEL_GEN(dev_priv) >= 9) {
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switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
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return DP_TRAIN_PRE_EMPH_LEVEL_3;
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@ -3015,7 +3016,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
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default:
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return DP_TRAIN_PRE_EMPH_LEVEL_0;
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}
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} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
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return DP_TRAIN_PRE_EMPH_LEVEL_3;
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@ -3027,7 +3028,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
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default:
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return DP_TRAIN_PRE_EMPH_LEVEL_0;
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}
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} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
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return DP_TRAIN_PRE_EMPH_LEVEL_3;
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@ -3039,7 +3040,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
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default:
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return DP_TRAIN_PRE_EMPH_LEVEL_0;
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}
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} else if (IS_GEN7(dev) && port == PORT_A) {
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} else if (IS_GEN7(dev_priv) && port == PORT_A) {
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switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
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return DP_TRAIN_PRE_EMPH_LEVEL_2;
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@ -5648,7 +5649,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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/* intel_dp vfuncs */
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if (INTEL_INFO(dev)->gen >= 9)
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intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
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else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
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else if (HAS_PCH_SPLIT(dev_priv))
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intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
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@ -2157,7 +2157,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
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}
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}
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} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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uint64_t sskpd = I915_READ64(MCH_SSKPD);
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wm[0] = (sskpd >> 56) & 0xFF;
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@ -2205,12 +2205,14 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
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int ilk_wm_max_level(const struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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/* how many WM levels are we expecting */
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if (INTEL_INFO(dev)->gen >= 9)
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if (INTEL_GEN(dev_priv) >= 9)
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return 7;
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else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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return 4;
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else if (INTEL_INFO(dev)->gen >= 6)
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else if (INTEL_GEN(dev_priv) >= 6)
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return 3;
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else
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return 2;
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@ -2393,7 +2395,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
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memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
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pipe_wm->wm[0] = pipe_wm->raw_wm[0];
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
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if (!ilk_validate_pipe_wm(dev, pipe_wm))
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@ -2580,7 +2582,7 @@ static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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return 2 * level;
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else
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return dev_priv->wm.pri_latency[level];
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@ -2804,7 +2806,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
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I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
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if (dirty & WM_DIRTY_DDB) {
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if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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val = I915_READ(WM_MISC);
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if (results->partitioning == INTEL_DDB_PART_1_2)
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val &= ~WM_MISC_DATA_PARTITION_5_6;
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@ -4415,7 +4417,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
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};
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hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
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memset(active, 0, sizeof(*active));
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@ -4623,7 +4625,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
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hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
|
||||
}
|
||||
|
||||
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
||||
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
||||
hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
|
||||
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
|
||||
else if (IS_IVYBRIDGE(dev_priv))
|
||||
|
|
|
@ -827,14 +827,14 @@ void intel_psr_init(struct drm_device *dev)
|
|||
|
||||
/* Per platform default */
|
||||
if (i915.enable_psr == -1) {
|
||||
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
||||
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
||||
i915.enable_psr = 1;
|
||||
else
|
||||
i915.enable_psr = 0;
|
||||
}
|
||||
|
||||
/* Set link_standby x link_off defaults */
|
||||
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
||||
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
||||
/* HSW and BDW require workarounds that we don't implement. */
|
||||
dev_priv->psr.link_standby = false;
|
||||
else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
||||
|
|
|
@ -288,7 +288,6 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
|
|||
static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct pci_dev *pdev = dev_priv->drm.pdev;
|
||||
struct drm_device *dev = &dev_priv->drm;
|
||||
|
||||
/*
|
||||
* After we re-enable the power well, if we touch VGA register 0x3d5
|
||||
|
@ -304,7 +303,7 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
|
|||
outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
|
||||
vga_put(pdev, VGA_RSRC_LEGACY_IO);
|
||||
|
||||
if (IS_BROADWELL(dev))
|
||||
if (IS_BROADWELL(dev_priv))
|
||||
gen8_irq_power_well_post_enable(dev_priv,
|
||||
1 << PIPE_C | 1 << PIPE_B);
|
||||
}
|
||||
|
|
|
@ -542,12 +542,12 @@ ivb_update_plane(struct drm_plane *plane,
|
|||
if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
|
||||
sprctl |= SPRITE_TILED;
|
||||
|
||||
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
||||
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
||||
sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
|
||||
else
|
||||
sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
|
||||
|
||||
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
||||
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
||||
sprctl |= SPRITE_PIPE_CSC_ENABLE;
|
||||
|
||||
/* Sizes are 0 based */
|
||||
|
@ -566,7 +566,7 @@ ivb_update_plane(struct drm_plane *plane,
|
|||
sprctl |= SPRITE_ROTATE_180;
|
||||
|
||||
/* HSW and BDW does this automagically in hardware */
|
||||
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
|
||||
if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
|
||||
x += src_w;
|
||||
y += src_h;
|
||||
}
|
||||
|
@ -590,7 +590,7 @@ ivb_update_plane(struct drm_plane *plane,
|
|||
|
||||
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
|
||||
* register */
|
||||
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
||||
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
||||
I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
|
||||
else if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
|
||||
I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
|
||||
|
|
Loading…
Reference in a new issue