ath9k: Define bus agnostic bluetooth coex prep helper
We disable ASPM when enabling bluetooth coexistance. Disabling ASPM is a bus specific operation. In the future other buses may support bluetooth coexistance, an example is USB. To this end move the current routine which disables ASPM into pci.c, and declare it the PCI bt_coex_prep() helper. Additionally, since ASPM is a PCI-Express primitive ensure we don't ever try to muck with ASPM registers on non PCI-express devices. This also cleans up hw.c to not include bus specific headers or utilities. Cc: Vasanthakumar Thiagarajan <vasanth@atheros.com> Cc: Stephen Chen <stephen.chen@atheros.com> Cc: Zhifeng Cai <zhifeng.cai@atheros.com> Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -545,6 +545,7 @@ struct ath_bus_ops {
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void (*read_cachesize)(struct ath_softc *sc, int *csz);
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void (*read_cachesize)(struct ath_softc *sc, int *csz);
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void (*cleanup)(struct ath_softc *sc);
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void (*cleanup)(struct ath_softc *sc);
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bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data);
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bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data);
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void (*bt_coex_prep)(struct ath_softc *sc);
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};
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};
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struct ath_wiphy;
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struct ath_wiphy;
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@ -16,7 +16,6 @@
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#include <linux/io.h>
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#include <linux/io.h>
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#include <asm/unaligned.h>
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#include <asm/unaligned.h>
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#include <linux/pci.h>
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#include "hw.h"
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#include "hw.h"
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#include "ath9k.h"
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#include "ath9k.h"
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@ -4294,16 +4293,3 @@ void ath_gen_timer_isr(struct ath_hw *ah)
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timer->trigger(timer->arg);
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timer->trigger(timer->arg);
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}
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}
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}
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}
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/*
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* Primitive to disable ASPM
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*/
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void ath_pcie_aspm_disable(struct ath_softc *sc)
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{
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struct pci_dev *pdev = to_pci_dev(sc->dev);
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u8 aspm;
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pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
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aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
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pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
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}
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@ -679,5 +679,4 @@ u32 ath9k_hw_gettsf32(struct ath_hw *ah);
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#define ATH_PCIE_CAP_LINK_L0S 1
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#define ATH_PCIE_CAP_LINK_L0S 1
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#define ATH_PCIE_CAP_LINK_L1 2
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#define ATH_PCIE_CAP_LINK_L1 2
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void ath_pcie_aspm_disable(struct ath_softc *sc);
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#endif
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#endif
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@ -2241,7 +2241,8 @@ static int ath9k_start(struct ieee80211_hw *hw)
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AR_STOMP_LOW_WLAN_WGHT);
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AR_STOMP_LOW_WLAN_WGHT);
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ath9k_hw_btcoex_enable(ah);
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ath9k_hw_btcoex_enable(ah);
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ath_pcie_aspm_disable(sc);
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if (sc->bus_ops->bt_coex_prep)
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sc->bus_ops->bt_coex_prep(sc);
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if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
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if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
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ath9k_btcoex_timer_resume(sc);
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ath9k_btcoex_timer_resume(sc);
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}
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}
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@ -75,10 +75,27 @@ static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
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return true;
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return true;
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}
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}
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/*
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* Bluetooth coexistance requires disabling ASPM.
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*/
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static void ath_pci_bt_coex_prep(struct ath_softc *sc)
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{
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struct pci_dev *pdev = to_pci_dev(sc->dev);
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u8 aspm;
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if (!pdev->is_pcie)
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return;
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pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
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aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
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pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
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}
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static struct ath_bus_ops ath_pci_bus_ops = {
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static struct ath_bus_ops ath_pci_bus_ops = {
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.read_cachesize = ath_pci_read_cachesize,
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.read_cachesize = ath_pci_read_cachesize,
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.cleanup = ath_pci_cleanup,
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.cleanup = ath_pci_cleanup,
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.eeprom_read = ath_pci_eeprom_read,
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.eeprom_read = ath_pci_eeprom_read,
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.bt_coex_prep = ath_pci_bt_coex_prep,
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};
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};
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static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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