[PATCH] ARM: 2691/1: PXA27x sleep fixes take 2
Patch from Todd Poynor PXA27x sleep fixes: * set additional sleep/wakeup registers for Mainstone boards. * move CKEN=0 to pxa25x-specific code; that value is harmful on pxa27x. * save/restore additional registers, including some found necessary for C5 processors and/or newer blob versions. * enable future support of additional sleep modes for PXA27x (eg, standby, deep sleep). * split off cpu-specific sleep processing between pxa27x and pxa25x into separate files (partly in preparation for additional sleep modes). Includes fixes from David Burrage. Signed-off-by: Todd Poynor Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -304,6 +304,15 @@ static void __init mainstone_map_io(void)
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PWER = 0xC0000002;
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PRER = 0x00000002;
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PFER = 0x00000002;
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/* for use I SRAM as framebuffer. */
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PSLR |= 0xF04;
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PCFR = 0x66;
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/* For Keypad wakeup. */
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KPC &=~KPC_ASACT;
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KPC |=KPC_AS;
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PKWR = 0x000FD000;
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/* Need read PKWR back after set it. */
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PKWR;
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}
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MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
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@ -29,9 +29,6 @@
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*/
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#undef DEBUG
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extern void pxa_cpu_suspend(void);
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extern void pxa_cpu_resume(void);
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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@ -63,6 +60,12 @@ enum { SLEEP_SAVE_START = 0,
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SLEEP_SAVE_ICMR,
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SLEEP_SAVE_CKEN,
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#ifdef CONFIG_PXA27x
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SLEEP_SAVE_MDREFR,
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SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
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SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
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#endif
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SLEEP_SAVE_CKSUM,
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SLEEP_SAVE_SIZE
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@ -75,9 +78,7 @@ static int pxa_pm_enter(suspend_state_t state)
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unsigned long checksum = 0;
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struct timespec delta, rtc;
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int i;
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if (state != PM_SUSPEND_MEM)
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return -EINVAL;
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extern void pxa_cpu_pm_enter(suspend_state_t state);
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#ifdef CONFIG_IWMMXT
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/* force any iWMMXt context to ram **/
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@ -100,16 +101,17 @@ static int pxa_pm_enter(suspend_state_t state)
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SAVE(GAFR2_L); SAVE(GAFR2_U);
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#ifdef CONFIG_PXA27x
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SAVE(MDREFR);
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SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
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SAVE(GAFR3_L); SAVE(GAFR3_U);
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SAVE(PWER); SAVE(PCFR); SAVE(PRER);
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SAVE(PFER); SAVE(PKWR);
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#endif
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SAVE(ICMR);
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ICMR = 0;
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SAVE(CKEN);
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CKEN = 0;
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SAVE(PSTR);
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/* Note: wake up source are set up in each machine specific files */
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@ -123,16 +125,13 @@ static int pxa_pm_enter(suspend_state_t state)
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/* Clear sleep reset status */
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RCSR = RCSR_SMR;
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/* set resume return address */
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PSPR = virt_to_phys(pxa_cpu_resume);
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/* before sleeping, calculate and save a checksum */
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for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
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checksum += sleep_save[i];
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sleep_save[SLEEP_SAVE_CKSUM] = checksum;
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/* *** go zzz *** */
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pxa_cpu_suspend();
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pxa_cpu_pm_enter(state);
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/* after sleeping, validate the checksum */
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checksum = 0;
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@ -145,7 +144,7 @@ static int pxa_pm_enter(suspend_state_t state)
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LUB_HEXLED = 0xbadbadc5;
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#endif
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while (1)
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pxa_cpu_suspend();
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pxa_cpu_pm_enter(state);
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}
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/* ensure not to come back here if it wasn't intended */
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@ -162,8 +161,11 @@ static int pxa_pm_enter(suspend_state_t state)
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RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
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#ifdef CONFIG_PXA27x
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RESTORE(MDREFR);
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RESTORE(GAFR3_L); RESTORE(GAFR3_U); RESTORE_GPLEVEL(3);
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RESTORE(GPDR3); RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
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RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
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RESTORE(PFER); RESTORE(PKWR);
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#endif
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PSSR = PSSR_RDH | PSSR_PH;
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@ -197,7 +199,9 @@ unsigned long sleep_phys_sp(void *sp)
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*/
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static int pxa_pm_prepare(suspend_state_t state)
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{
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return 0;
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extern int pxa_cpu_pm_prepare(suspend_state_t state);
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return pxa_cpu_pm_prepare(state);
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}
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/*
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@ -102,3 +102,32 @@ unsigned int get_lcdclk_frequency_10khz(void)
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}
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EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
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int pxa_cpu_pm_prepare(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_MEM:
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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void pxa_cpu_pm_enter(suspend_state_t state)
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{
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extern void pxa_cpu_suspend(unsigned int);
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extern void pxa_cpu_resume(void);
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CKEN = 0;
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switch (state) {
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case PM_SUSPEND_MEM:
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/* set resume return address */
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PSPR = virt_to_phys(pxa_cpu_resume);
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pxa_cpu_suspend(3);
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break;
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}
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}
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@ -120,6 +120,38 @@ EXPORT_SYMBOL(get_clk_frequency_khz);
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EXPORT_SYMBOL(get_memclk_frequency_10khz);
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EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
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int pxa_cpu_pm_prepare(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_MEM:
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return 0;
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default:
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return -EINVAL;
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}
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}
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void pxa_cpu_pm_enter(suspend_state_t state)
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{
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extern void pxa_cpu_standby(void);
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extern void pxa_cpu_suspend(unsigned int);
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extern void pxa_cpu_resume(void);
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CKEN = CKEN22_MEMC | CKEN9_OSTIMER;
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/* ensure voltage-change sequencer not initiated, which hangs */
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PCFR &= ~PCFR_FVC;
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/* Clear edge-detect status register. */
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PEDR = 0xDF12FE1B;
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switch (state) {
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case PM_SUSPEND_MEM:
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/* set resume return address */
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PSPR = virt_to_phys(pxa_cpu_resume);
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pxa_cpu_suspend(3);
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break;
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}
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}
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/*
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* device registration specific to PXA27x.
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