ath5k: review RX descriptor functions
Reviewed RX descriptor functions against the HAL sources. Some minor changes: - check size before making changes to the descriptor - whitespace - add comments about 5210 timestamps. this needs to be adressed later! - FIFO overrun error only available on 5210 - rs_phyerr should not be OR'ed - clear the whole ath5k_rx_status structure before using, instead of zeroing specific fields. Signed-off-by: Bruno Randolf <br1@einfach.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -499,10 +499,11 @@ int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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*/
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memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
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if (unlikely(size & ~AR5K_DESC_RX_CTL1_BUF_LEN))
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return -EINVAL;
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/* Setup descriptor */
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rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
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if (unlikely(rx_ctl->rx_control_1 != size))
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return -EINVAL;
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if (flags & AR5K_RXDESC_INTREQ)
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rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
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@ -522,9 +523,11 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
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/* No frame received / not ready */
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if (unlikely(!(rx_status->rx_status_1 &
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AR5K_5210_RX_DESC_STATUS1_DONE)))
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AR5K_5210_RX_DESC_STATUS1_DONE)))
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return -EINPROGRESS;
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memset(rs, 0, sizeof(struct ath5k_rx_status));
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/*
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* Frame receive status
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*/
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@ -536,7 +539,11 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
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AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
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rs->rs_more = !!(rx_status->rx_status_0 &
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AR5K_5210_RX_DESC_STATUS0_MORE);
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/* TODO: this timestamp is 13 bit, later on we assume 15 bit */
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/* TODO: this timestamp is 13 bit, later on we assume 15 bit!
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* also the HAL code for 5210 says the timestamp is bits [10..22] of the
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* TSF, and extends the timestamp here to 15 bit.
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* we need to check on 5210...
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*/
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rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
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AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
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@ -548,9 +555,6 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
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AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210)
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? 2 : 1;
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rs->rs_status = 0;
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rs->rs_phyerr = 0;
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/*
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* Key table status
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*/
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@ -564,19 +568,21 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
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* Receive/descriptor errors
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*/
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if (!(rx_status->rx_status_1 &
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AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
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AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
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if (rx_status->rx_status_1 &
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AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
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rs->rs_status |= AR5K_RXERR_CRC;
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if (rx_status->rx_status_1 &
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AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210)
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/* only on 5210 */
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if ((ah->ah_version == AR5K_AR5210) &&
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(rx_status->rx_status_1 &
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AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210))
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rs->rs_status |= AR5K_RXERR_FIFO;
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if (rx_status->rx_status_1 &
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AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
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rs->rs_status |= AR5K_RXERR_PHY;
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rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
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rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
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AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
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}
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@ -604,6 +610,8 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
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AR5K_5212_RX_DESC_STATUS1_DONE)))
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return -EINPROGRESS;
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memset(rs, 0, sizeof(struct ath5k_rx_status));
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/*
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* Frame receive status
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*/
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@ -619,8 +627,6 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
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AR5K_5212_RX_DESC_STATUS0_MORE);
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rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
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AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
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rs->rs_status = 0;
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rs->rs_phyerr = 0;
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/*
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* Key table status
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@ -643,7 +649,7 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
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if (rx_status->rx_status_1 &
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AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
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rs->rs_status |= AR5K_RXERR_PHY;
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rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
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rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
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AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE);
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ath5k_ani_phy_error_report(ah, rs->rs_phyerr);
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}
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