clocksource: cadence_ttc: Use readl/writel_relaxed instead of __raw
For supporting ARM big-endian is necessary to use
proper IO endianess accessors.
Based on Ben Dooks BE guide.
Similar conversion is done here:
"mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel}"
(sha1: 5733c38ae3
)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
parent
a99e2ad37f
commit
87ab4361be
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@ -118,11 +118,11 @@ static void ttc_set_interval(struct ttc_timer *timer,
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u32 ctrl_reg;
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/* Disable the counter, set the counter value and re-enable counter */
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ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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__raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
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writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
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/*
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* Reset the counter (0x10) so that it starts from 0, one-shot
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@ -130,7 +130,7 @@ static void ttc_set_interval(struct ttc_timer *timer,
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*/
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ctrl_reg |= CNT_CNTRL_RESET;
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ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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}
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/**
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@ -147,7 +147,7 @@ static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
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struct ttc_timer *timer = &ttce->ttc;
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/* Acknowledge the interrupt and call event handler */
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__raw_readl(timer->base_addr + TTC_ISR_OFFSET);
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readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
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ttce->ce.event_handler(&ttce->ce);
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@ -163,13 +163,13 @@ static cycle_t __ttc_clocksource_read(struct clocksource *cs)
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{
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struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
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return (cycle_t)__raw_readl(timer->base_addr +
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return (cycle_t)readl_relaxed(timer->base_addr +
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TTC_COUNT_VAL_OFFSET);
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}
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static u64 notrace ttc_sched_clock_read(void)
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{
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return __raw_readl(ttc_sched_clock_val_reg);
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return readl_relaxed(ttc_sched_clock_val_reg);
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}
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/**
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@ -211,17 +211,17 @@ static void ttc_set_mode(enum clock_event_mode mode,
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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ctrl_reg = __raw_readl(timer->base_addr +
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ctrl_reg = readl_relaxed(timer->base_addr +
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TTC_CNT_CNTRL_OFFSET);
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ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg,
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writel_relaxed(ctrl_reg,
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timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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break;
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case CLOCK_EVT_MODE_RESUME:
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ctrl_reg = __raw_readl(timer->base_addr +
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ctrl_reg = readl_relaxed(timer->base_addr +
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TTC_CNT_CNTRL_OFFSET);
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ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg,
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writel_relaxed(ctrl_reg,
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timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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break;
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}
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@ -266,8 +266,8 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
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* of an abort.
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*/
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ttccs->scale_clk_ctrl_reg_old =
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__raw_readl(ttccs->ttc.base_addr +
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TTC_CLK_CNTRL_OFFSET);
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readl_relaxed(ttccs->ttc.base_addr +
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TTC_CLK_CNTRL_OFFSET);
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psv = (ttccs->scale_clk_ctrl_reg_old &
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TTC_CLK_CNTRL_PSV_MASK) >>
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@ -291,8 +291,8 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
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return NOTIFY_DONE;
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/* scale up: adjust divider now - before frequency change */
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__raw_writel(ttccs->scale_clk_ctrl_reg_new,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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break;
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}
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case POST_RATE_CHANGE:
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@ -301,8 +301,8 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
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return NOTIFY_OK;
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/* scale down: adjust divider now - after frequency change */
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__raw_writel(ttccs->scale_clk_ctrl_reg_new,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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break;
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case ABORT_RATE_CHANGE:
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@ -311,8 +311,8 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
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return NOTIFY_OK;
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/* restore original register value */
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__raw_writel(ttccs->scale_clk_ctrl_reg_old,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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/* fall through */
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default:
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return NOTIFY_DONE;
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@ -359,10 +359,10 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
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* with no interrupt and it rolls over at 0xFFFF. Pre-scale
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* it by 32 also. Let it start running now.
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*/
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__raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
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__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
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writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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__raw_writel(CNT_CNTRL_RESET,
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writel_relaxed(CNT_CNTRL_RESET,
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ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
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err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
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@ -438,10 +438,10 @@ static void __init ttc_setup_clockevent(struct clk *clk,
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* is prescaled by 32 using the interval interrupt. Leave it
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* disabled for now.
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*/
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__raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
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__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
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writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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__raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
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writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
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err = request_irq(irq, ttc_clock_event_interrupt,
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IRQF_TIMER, ttcce->ce.name, ttcce);
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@ -490,7 +490,7 @@ static void __init ttc_timer_init(struct device_node *timer)
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BUG();
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}
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clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
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clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
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clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
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clk_cs = of_clk_get(timer, clksel);
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if (IS_ERR(clk_cs)) {
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@ -498,7 +498,7 @@ static void __init ttc_timer_init(struct device_node *timer)
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BUG();
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}
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clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
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clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
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clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
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clk_ce = of_clk_get(timer, clksel);
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if (IS_ERR(clk_ce)) {
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