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clk: at91: fix recalc_rate implementation of PLL driver 

Use the cached values to calculate PLL rate instead of the register values.
This is required to prevent erroneous PLL rate return when the PLL rate
has been configured but the PLL is not prepared yet.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
wifi-calibration
Boris BREZILLON 2014-09-02 09:50:16 +02:00 committed by Mike Turquette
parent 3ef9dd2bab
commit 87e2ed338f
1 changed files with 3 additions and 8 deletions
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11
drivers/clk/at91/clk-pll.c
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@ -151,16 +151,11 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_pll *pll = to_clk_pll(hw);
const struct clk_pll_layout *layout = pll->layout;
struct at91_pmc *pmc = pll->pmc;
int offset = PLL_REG(pll->id);
u32 tmp = pmc_read(pmc, offset) & layout->pllr_mask;
u8 div = PLL_DIV(tmp);
u16 mul = PLL_MUL(tmp, layout);
if (!div || !mul)
if (!pll->div || !pll->mul)
return 0;
return (parent_rate * (mul + 1)) / div;
return (parent_rate / pll->div) * (pll->mul + 1);
}
static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,