MIPS: IP27: Fix typo
Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13320/ Patchwork: https://patchwork.linux-mips.org/patch/13335/ Patchwork: https://patchwork.linux-mips.org/patch/13336/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -64,7 +64,7 @@ static inline void plat_post_dma_flush(struct device *dev)
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static inline int plat_device_is_coherent(struct device *dev)
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{
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return 1; /* IP27 non-cohernet mode is unsupported */
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return 1; /* IP27 non-coherent mode is unsupported */
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}
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#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */
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@ -33,9 +33,9 @@ static u32 emulate_ioc3_cfg(int where, int size)
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* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
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* not really documented, so right now I can't write code which uses it.
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* Therefore we use type 0 accesses for now even though they won't work
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* correcly for PCI-to-PCI bridges.
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* correctly for PCI-to-PCI bridges.
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*
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* The function is complicated by the ultimate brokeness of the IOC3 chip
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* The function is complicated by the ultimate brokenness of the IOC3 chip
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* which is used in SGI systems. The IOC3 can only handle 32-bit PCI
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* accesses and does only decode parts of it's address space.
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*/
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@ -105,7 +105,7 @@ static void hub_setup_prb(nasid_t nasid, int prbnum, int credits)
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prb.iprb_ff = force_fire_and_forget ? 1 : 0;
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/*
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* Set the appropriate number of PIO cresits for the widget.
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* Set the appropriate number of PIO credits for the widget.
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*/
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prb.iprb_xtalkctr = credits;
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